JESD204 Interface Framework
The JESD204, JESD204A, JESD204B and the JESD204C data converter serial interface standard was created through the JEDEC committee to standardize and reduce the number of data inputs/outputs between high-speed data converters and other devices, such as FPGAs (field-programmable gate arrays). Fewer interconnects simplifies layout and allows smaller form factor realization without impacting overall system performance. These attributes are important to address the system size and cost constraints of a range of high speed ADC applications, including wireless infrastructure (GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA) transceiver architectures, software-defined radios, portable instrumentation, medical ultrasound equipment, and Mil/Aero applications such as radar and secure communications. Analog Devices is an original participating member of the JEDEC JESD204 standards committee and we have concurrently developed compliant data converter technology and tools, and a comprehensive product roadmap to fully enable our customers to take advantage of this significant interfacing breakthrough.
Analog Devices supplies a full-stack supporting JESD204B/C which provides a fully integrated system level experience. This solution includes
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FPGA HDL for interfacing JESD204B/C ADCs, DACs, and RF Transceivers
Software to configure the converter devices and FPGA HDL peripherals
How to Obtain a License
When customers and partners download software from github, or e-mail downloaded software to someone, they are obligated to comply to the terms and conditions of the Software License Agreement. The core is released under two difference licenses. You may choose either:
Commercial licenses may be purchased from Analog Devices, Inc. or any authorized distributor by ordering
IP-JESD204. This will allow you to use the core in a closed system.
GPL 2, this allows you to use the core for any purpose, but you must release anything else that links to the JESD204 core (this would normally be your algorithmic IP). You do not need to sign anything purchase anything to use the JESD204 core under the
GPL license.
There is only one core, the only difference is the license and support. If you have a question about the license: you can email jesd204 [dash] licensing [at] analog [dot] com.
FPGA HDL Support
The JESD204B/C standard defines multiple layers, each layer being responsible for a particular function. The Analog Devices JESD204B/C HDL solution follows the standard here and defines 4 layers. Physical layer, link layer, transport layer and application layer. For the first three layers Analog Devices provides standard components that can be linked up to provide a full JESD204B/C protocol processing chain.
Depending on the FPGA and converter combinations that are being interfaced different components can be chosen for the physical and transport layer. The FPGA defines which physical layer component should be used and the interfaced converter defines which transport layer component should be used.
The link layer component is selected based on the direction of the JESD204B/C link.
The application layer is user defined and can be used to implement application specific signal processing.
Physical Layer
Physical layer peripherals are responsible for interfacing and configuring the high-speed serial transceivers.
Currently we have support for GTXE2, GTHE3, GTHE4, GTYE4 for Xilinx and Arria 10 transceivers for Intel.
AXI_ADXCVR: JESD204B Gigabit Transceiver Register Configuration Peripheral
UTIL_ADXCVR: JESD204B Gigabit Transceiver Interface Peripheral for Xilinx FPGAs
Link Layer
Link layer peripherals are responsible for JESD204B/C protocol handling, including scrambling/descrambling, lane alignment, character replacement and alignment monitoring.
Transport Layer
Transport layer peripherals are responsible for converter specific data framing and de-framing.
Interfaces
Interfaces are a well-defined collection of wires that are used to communicate between components. The following interfaces are used to connect components of the HDL JESD204B/C processing stack.
Software Support
Linux
No-OS
Tutorial
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Checkout the
HDL Source, and then build either one of:
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Example Projects
Technical Articles
JESD204B Analog-to-Digital Converters
AD6673: 80
MHz Bandwidth, Dual IF Receiver
AD6674: 385
MHz BW IF Diversity Receiver
AD6676: Wideband IF Receiver Subsystem
AD6677: 80
MHz Bandwidth, IF Receiver
AD6684: 135
MHz Quad IF Receiver
AD6688: RF Diversity and 1.2GHz BW Observation Receiver
AD9208: 14-Bit, 3GSPS, JESD204B, Dual Analog-to-Digital Converter
AD9234: 12-Bit, 1 GSPS/500
MSPS JESD204B, Dual Analog-to-Digital Converter
AD9250: 14-Bit, 170
MSPS/250
MSPS, JESD204B, Dual Analog-to-Digital Converter
AD9625: 12-Bit, 2.6 GSPS/2.5 GSPS/2.0 GSPS, 1.3
V/2.5
V Analog-to-Digital Converter
AD9656: Quad, 16-Bit, 125
MSPS JESD204B 1.8
V Analog-to-Digital Converter
AD9680: 14-Bit, 1.25 GSPS/1 GSPS/820
MSPS/500
MSPS JESD204B, Dual Analog-to-Digital Converter
AD9683: 14-Bit, 170
MSPS/250
MSPS, JESD204B, Analog-to-Digital Converter
AD9690: 14-Bit, 500
MSPS / 1 GSPS JESD204B, Analog-to-Digital Converter
AD9691: 14-Bit, 1.25 GSPS JESD204B, Dual Analog-to-Digital Converter
AD9694: 14-Bit, 500
MSPS JESD204B, Quad Analog-to-Digital Converter
AD9083: 16-Channel, 125
MHz Bandwidth, JESD204B Analog-to-Digital Converter
JESD204B Digital-to-Analog Converters
AD9135: Dual, 11-Bit, high dynamic, 2.8 GSPS, TxDAC+® Digital-to-Analog Converter
AD9136: Dual, 16-Bit, 2.8 GSPS, TxDAC+® Digital-to-Analog Converter
AD9144: Quad, 16-Bit, 2.8 GSPS, TxDAC+® Digital-to-Analog Converter
AD9152: Dual, 16-Bit, 2.25 GSPS, TxDAC+ Digital-to-Analog Converter
AD9154: Quad, 16-Bit, 2.4 GSPS, TxDAC+® Digital-to-Analog Converter
AD9161: 11-Bit, 12 GSPS, RF Digital-to-Analog Converter
AD9162: 16-Bit, 12 GSPS, RF Digital-to-Analog Converter
AD9163: 16-Bit, 12 GSPS, RF DAC and Digital Upconverter
AD9164: 16-Bit, 12 GSPS, RF DAC and Direct Digital Synthesizer
AD9172: Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers
AD9173: Dual, 16-Bit, 12.6 GSPS RF DAC with Channelizers
AD9174: Dual, 16-Bit, 12.6 GSPS RF DAC and Direct Digital Synthesizer
AD9175: Dual, 11-Bit/16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers
AD9176: Dual, 16-Bit, 12.6 GSPS RF DAC with Wideband Channelizers
JESD204B RF Transceivers
AD9371: SDR Integrated, Dual RF Transceiver with Observation Path
AD9375: SDR Integrated, Dual RF Transceiver with Observation Path and DPD
ADRV9009: SDR Integrated, Dual RF Transceiver with Observation Path
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ADRV9008-2: SDR Integrated, Dual RF Transmitter with Observation Path
JESD204B/C Mixed-Signal Front Ends
AD9081: MxFE™ Quad, 16-Bit, 12GSPS RFDAC and Quad, 12-Bit, 4GSPS RFADC
AD9082: MxFE™ QUAD, 16-Bit, 12GSPS RFDAC and DUAL, 12-Bit, 6GSPS RFADC
JESD204B Clocking Solutions
AD9528: JESD204B Clock Generator with 14 LVDS/HSTL Outputs
HMC7043: High Performance, 3.2
GHz, 14-Output Fanout Buffer
HMC7044: High Performance, 3.2
GHz, 14-Output Jitter Attenuator with JESD204B
LTC6952: Ultralow Jitter, 4.5GHz
PLL, JESD204B/JESD204C