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This version (14 Jan 2021 05:36) was approved by Robin Getz.The Previously approved version (02 Dec 2020 14:00) is available.Diff

Generic JESD204B block designs

Using the generic building blocks from the ADI IP library together with the JESD framework, parametrizable block designs can be built to interface ADI DACs and ADCs in various JESD modes.

Typically projects are built and configured to exercise the DAC/ADC devices maximum capability using all available lanes, this corresponds to a single JESD operation mode. In order to switch to other modes, the generic block designs can be reconfigured by changing its parameters. These parameters map to the JESD link parameters. See the example below taken from this block design:

# TX parameters
set TX_NUM_OF_LANES 4      ; # L
set TX_NUM_OF_CONVERTERS 4 ; # M
set TX_SAMPLES_PER_FRAME 1 ; # S
set TX_SAMPLE_WIDTH 16     ; # N/NP
 
set TX_SAMPLES_PER_CHANNEL 2 ; # L * 32 / (M * N)
Changing the number of lanes parameter will affect the top level file, as the constraints file. If the number of lanes is reduced both files must be updated to remove references to the unused lanes.
L Lane Count
M Converter Count
F Octets per Frame per Lane
S Samples per Converter per Frame
NP Total Number of Bits per Sample
N Converter Resolution
K Frames per Multiframe
HD High Density User Data Format
E Number of multiblocks in an extended multiblock
In JESD links the following equation must hold:

M*S*NP = L*F*8 or M/L = (F/S) * (8/NP)

Based on this equation a missing parameter can be calculated from the others.

Generic Tx path

The below diagram presents a generic JESD Tx path from application layer to the FPGA boundary. The application layer is connected to the Tx path through the DAC Transport Layer which for each converter accepts a data beat on every cycle. The width of data beat is defined by the DPW (data path width) and NP parameter. DPW represents the number of samples per converter per data clock cycle. DPW must be a natural number (greater than one and a whole number).

On each clock cycle the Link Layer accepts 32 bits per every lane as a constraint from the physical layer that is configured to 32bit mode. This means that for each clock cycle the application layer must provide enough samples for each converter so the transport layer can fill 32 bits of data for each lane. Due this constraint the following equation must hold: L*32 = M*NP*DPW

In such design the following constraints apply to the transport layer:

  • F = {1, 2, 4}
  • NP = {8, 16}

More information on the DAC Transport layer can be found in DAC JESD204B Transport Peripheral page.

The Link layer consists from L number of lanes which form the link. More information on the Tx Link layer can be found in JESD204B Transmit Peripheral page.

In this mode the Transport Layer will output two frames in every clock cycle. 32 bits / (F*8) = 2;
The application layer must provide 8 samples each cycle to be able to fill the 2 frames. DPW = (L*32) / (M*NP) = (4*32) / (1*16) = 128/16 = 8

In this mode the Transport Layer will output two frames in every clock cycle. 32 bits / (F*8) = 2;
The application layer must provide 8 samples each cycle to be able to fill the 2 frames. DPW = (L*32) / (M*NP) = (4*32) / (4*16) = 128/64 = 2

Generic Rx path

The below diagram presents a generic JESD Rx path. The application layer is connected to the Rx path through the ADC Transport Layer which for each converter generates a data beat on every cycle. The width of data beat is defined by the DPW (data path width) and NP parameter. DPW represents the number of samples per converter per data clock cycle. DPW must be a natural number (greater than one and a whole number).

On each clock cycle the Link Layer generates 32 bits per every lane as it is constrained from the physical layer that is configured to 32bit mode. This means that for each clock cycle the application layer must accept enough samples for each converter so the transport layer use 32 bits of data from each lane.

In such design the following constraints apply to the transport layer:

  • F = {1, 2, 4}
  • NP = {8, 16}

More information on the ADC Transport layer can be found in ADC JESD204B Transport Peripheral page.

The Link layer consists from L number of lanes which form the link. More information on the Rx Link layer can be found in JESD204B Receive Peripheral page.

In this mode the Transport Layer will accept two frames in every clock cycle. 32 bits / (F*8) = 2;
The application layer must accept 8 samples each cycle so the transport layer can deframe the 2 frames. DPW = (L*32) / (M*NP) = (4*32) / (1*16) = 128/16 = 8

Such a parametrizable block design was built for the ADRV9009 Prototyping Platform and can be found here.

JESD modes with F=8

In a period of LinkClk the Link layer always handles 32 bits per lane. The transport layer running at a same clock rate can fill the 32 bits with frames of 1,2 or 4 bytes.

However, for a link with L=1, M=4, NP=16 the minimum number of bytes per frame that must be supported is 8 (F=8)

F= M*S*NP / L*8 ; F = 8 * S

Tx path for F=8

In order to comply the requirement that in every DataClk period for each converter from the application layer a sample must be accepted (64 bits in this case), DataClk must be run with half the speed of the LinkClk.

The rate adaptation and synchronization is done with a gearbox which receives its clocks from a PLL that ensures its output clocks are in phase.

Rx path for F=8

The Rx path is similar to the Tx. In order the transport layer to produce a sample per converter in every clock cycle the Data clock must be ran at half of the link clock speed.

Such a parametrizable block design that supports also F=8 was built for the ADRV9009 Prototyping Platform and can be found here.

Support

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resources/fpga/docs/hdl/generic_jesd_bds.txt · Last modified: 14 Jan 2021 05:24 by Robin Getz