The AD9250 is a dual, 14-bit ADC with sampling speeds of up to 250 MSPS. It features a multistage, differential pipelined architecture with integrated output error correction logic. It supports wide bandwidth inputs for a variety of user-selectable input ranges. The AD9250 features JESD204B high speed serial interface.
The boards also feature the AD9517-1 for multi-output clock distribution with sub-picosecond jitter performance, along with an on-chip PLL and VCO. The devices may be clocked by either an internal clock source (optionally locked to an external reference) or an externally supplied sample clock.
It also features an external trigger input for customized sampling control. The card is mechanically and electrically compliant to the FMC standard (ANSI/VITA 57.1).
The reference design includes the device data capture via the JESD204B serial interface and the SPI interface. The samples are written to the external DDR-DRAM. It allows programming the device and monitoring it's internal registers via SPI.
The reference design is built on a microblaze based system parameterized for linux. A functional block diagram of the design is given below.
The reference design consists of a single JESD204B core and two identical instances of AD9250 pcores.
The AD9250 core consists of three functional modules, the ADC interface, a PN9/PN23 monitor and a DMA interface. The ADC interface captures and buffers data from the JESD204B core. The DMA interface then transfers the samples to the external DDR-DRAM. The capture is initiated by the software. The status of capture (overflow, over the range) are reported back to the software.
All the pcores have an AXI lite interface that allows control and monitoring of data generation and/or capture.
The reference design also includes HDMI cores for GTX eye scan.
The ADC sampling rate can vary from 40MHz to 250MHz. However, there are limitations imposed by the FPGA that may lower this range. In some cases, you may have to regenerate the cores for a different range. The reference design uses GTX (channel PLL) primitives and Xilinx's JESD204B core IP. The default design runs at 250MHz clock (5Gbps rate).
As of this writing, the GTX specification & switching characteristics may be found at:
The key switching characteristics are-
The reference clock has a range of 60MHz to 670MHz (700MHz). This limits the minimum sampling clock to 60MHz. Though it is NOT recommended, it is possible to use AD9517 to generate a 40MHz sampling clock to AD9250 and a 80MHz reference clock to the FPGA.
The line rate however, varies based on speed grade, package type and the use of CPLL vs QPLL. The CPLL supports rates between 0.5Gbps to 6.6Gbps (the core may have to be changed for rates less than 3.2Gbps (sampling rate 160MHz) - and the IP may not support all the combinations). Again, it is possible to run the device on a single lane at a higher rate (rather than 2 lanes each at a lower rate) to circumvent some of the troubles of line rate dependency on parametrization, package type and speed grade.
You must carefully evaluate these specifications against your requirements to run the design at a specific sampling frequency (or a range). As always, if you have any questions or run into any problems, ask help & support.
The AD9129 is a high performance 14-bit RF DAC supporting data rates up to 2.8GSPS. The DAC core is based on a quad-switch architecture that enables dual-edge clocking operation effectively increasing the DAC update rate to 5.6 GSPS when configured for mix-mode or 2x interpolation. Its high dynamic range and bandwidth enables multicarrier generation up to and beyond 4.2 GHz. The AD9129 features two 14bit LVDS parallel interface.
The following variations of this board are available.
|Part Number||ADC Channels||DAC Channels|
|FMC-176||4 (2 x AD9250)||2 (2 x AD9129)|
|FMC-230||2 (2 x AD9129)|
|AD-FMCJESDADC1-EBZ||4 (2 x AD9250)|
This reference design may be used as it is for FMC-176 and it's variations by selecting the appropriate number of DAC channels. It is also easy to port the design for other boards by removing one or more corresponding pcores. Also some devices may not be accessible depending on whether one choose to use LPC or HPC. To fully support both the DACs of the FMC-176, a carrier must have a fully populated HPC connector. The KC705 do not have a fully populated HPC.
The reference design includes (if enabled) RF generation via DDS and the SPI interface for the DACs. At the prompt just enter the number of DAC channels you have in your hardware setup. As an example, if you are using FMC-176 with KC705, simply enter '1' as the number of DAC channels. If you are using the ADC only boards, enter '0' as the number of DAC channels.
The quick start bit file also configures the AD9517 to generate a 2.5GHz clock to AD9129. It then generates a 333MHz tone for the DAC.
The DAC spectrum for a 333MHz tone is shown below.
It is possible to use an adapter board such as FMC-700 with KC705 to access both the DACs on a FMC-176 board. However, the routing delays of FMC-LPC pins to the FMC-700 will cause timing errors on DAC1 and you may see parity errors on the UART terminal.
The HDL Reference Designs and the no-OS Software can be downloaded from the Analog Devices github.
FPGA Reference Designs: