The AD9081-FMCA-EBZ reference design is a processor based (e.g. Microblaze) embedded system. The design consists from a receive and a transmit chain.
The receive chain transports the captured samples from ADC to the system memory (DDR). Before transferring the data to DDR the samples are stored in a buffer implemented on block rams from the FPGA fabric (util_adc_fifo). The space allocated in the buffer for each channel depends on the number of currently active channels. It goes up to M x 64k samples if a single channel is selected or 64k samples per channel if all channels are selected.
The transmit chain transports samples from the system memory to the DAC devices. Before streaming out the data to the DAC through the JESD link the samples first are loaded into a buffer (util_dac_fifo) which will cyclically stream the samples at the tx_device_clk data rate. The space allocated in the transmit buffer for each channel depends on the number of currently active channels. It goes up to M x 64k samples if a single channel is selected or 64k samples per channel if all channels are selected.
All cores from the receive and transmit chains are programmable through an AXI-Lite interface.
The transmit and receive chains can operate at different data rates having separate rx_device_clk/tx_device_clk and corresponding lane rates but must share the same reference clock.
Reference design location:
The block design supports parameters and scales based on it as shown on the below two examples.
The parameters for Rx or Tx links can be changed from the system_project.tcl :
# Parameter description: # JESD_MODE : used link layer encoder mode # 64B66B - 64b66b link layer defined in JESD 204C # 8B10B - 8b10b link layer defined in JESD 204B # # RX_RATE : line rate of the Rx link ( MxFE to FPGA ) # TX_RATE : line rate of the Tx link ( FPGA to MxFE ) # [RX/TX]_JESD_M : number of converters per link # [RX/TX]_JESD_L : number of lanes per link # [RX/TX]_JESD_NP : number of bits per sample, only 16 is supported # [RX/TX]_NUM_LINKS : number of links, 1 - single link; 2 - dual link. adi_project mxfe_zcu102 0 [list \ JESD_MODE 8B10B \ RX_JESD_M 8 \ RX_JESD_L 4 \ RX_JESD_S 1 \ RX_JESD_NP 16 \ RX_NUM_LINKS 1 \ TX_JESD_M 8 \ TX_JESD_L 4 \ TX_JESD_S 1 \ TX_JESD_NP 16 \ TX_NUM_LINKS 1 \ ]
For the parameter selection the following restrictions apply:
Following IPs are used in the block design:
|IP name||Wiki page|
|XCVR||UTIL_ADXCVR core for Xilinx devices|
|RX JESD LINK||JESD204B/C Link Receive Peripheral|
|TX JESD LINK||JESD204B/C Link Transmit Peripheral|
|RX JESD TPL||ADC JESD204B/C Transport Peripheral|
|TX JESD TPL||DAC JESD204B/C Transport Peripheral|
|UTIL CPACK||Channel CPACK Utility Core (util_cpack)|
|UTIL UPACK||Channel UNPACK Utility Core (util_upack)|
|AXI DMAC||High-Speed DMA Controller Peripheral|
The Rx links (ADC Path) operate with the following parameters:
The Tx links (DAC Path) operate with the following parameters:
The Rx links are set for full bandwidth mode and operate with the following parameters:
The Tx links are set for full bandwidth mode and operate with the following parameters:
Observation: In 2019_R2 release the Xilinx JESD Physical layer IP Core is used, however in newer versions it is replaced with ADI's util_adxcvr IP core.
The project must be built with the following parameters:
make JESD_MODE=64B66B \ RX_RATE=16.5 \ RX_PLL_SEL=2 \ TX_RATE=16.5 \ TX_PLL_SEL=2 \ REF_CLK_RATE=500 \ RX_JESD_M=2 \ RX_JESD_L=8 \ RX_JESD_S=2 \ RX_JESD_NP=16 \ TX_JESD_M=2 \ TX_JESD_L=8 \ TX_JESD_S=4 \ TX_JESD_NP=8
The Rx link is operating with the following parameters:
The Tx link is operating with the following parameters:
The clock sources depend on the in use carrier and are depicted on the below diagrams:
Due physical constraints Rx lanes are reordered as described in the following table. e.g physical lane 2 from ADC connects to logical lane 7 from the FPGA. Therefore the crossbar from the device must be set accordingly.
|ADC phy Lane||FPGA Rx lane|
Due physical constraints Tx lanes are reordered as described in the following table: e.g physical lane 2 from DAC connects to logical lane 7 from the FPGA. Therefore the crossbar from the device must be set accordingly.
|DAC phy Lane||FPGA Tx lane|
Analog Devices will provide limited online support for anyone using the reference design with Analog Devices components via the EngineerZone.