This tutorial will show in a step by step manner how to use the JESD204B Interface Framework to support a high speed data acquisition system using Analog Devices open source repositories.
JESD204B is a high-speed serial link for data converters between converter and logic device (FPGA/ASIC):
Latency can be defined as deterministic when the time from the input of the JESD204x transmitter to the output of the JESD204x receiver is consistently the same number of clock cycles. In parallel implementations, deterministic latency is rather simple – clocks are carried with the data. In serial implementations, multiple clock domains exist, which can cause nondeterminism. JESD204 and JESD204A do not contain provisions for guaranteeing deterministic latency.
JESD204B looks to address the deterministic latency issue by specifying three device subclasses:
The JESD204 Interface Framework is a system-level integrated HDL and software framework that handles system-level as well as component-level constraints and dependencies:
It is an integrated framework covering the whole stack on different facets of system design:
The JESD204B standard defines multiple layers, each layer being responsible for a particular function. The Analog Devices JESD204B HDL solution follows the standard here and defines 4 layers. Physical layer, link layer, transport layer and application layer. For the first three layers Analog Devices provides standard components that can be linked up to provide a full JESD204B protocol processing chain.
Depending on the FPGA and converter combinations that are being interfaced, different components can be chosen for the physical and transport layer. The FPGA defines which physical layer component should be used and the interfaced converter defines which transport layer component should be used.
The link layer component is selected based on the direction of the JESD204B link, as seen below.
The application layer is user defined and can be used to implement application specific signal processing.