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This version (05 Jun 2018 16:06) was approved by mhennerich.The Previously approved version (27 Mar 2018 11:08) is available.Diff

JESD204B Link Receive Peripheral

The Analog Devices JESD204B Link Receive Peripheral implements the link layer handling of a JESD204B receive logic device. This includes handling of the SYSREF and SYNC~ and controlling the link state machine accordingly as well as performing per lane descrambling and character replacement. It has been designed for interoperability with Analog Devices JESD204B ADC converter products.

To form a complete JESD204B receive logic device it has to be combined with a PHY layer and transport layer peripheral.

Features

  • Subclass 0 and Subclass 1 support
  • Deterministic Latency (for Subclass 1 operation)
  • Runtime re-configurability through memory-mapped register interface (AXI4-Lite)
  • Interrupts for event notification
  • Diagnostics
  • Max Lanerate: 15 Gbps
  • Low Latency
  • Independent per lane enable/disable

Utilization

Detailed Utilization (Click to expand)

Detailed Utilization (Click to expand)

Device Family NUM_LANES LUTs FFs
Intel Arria 10 1 TBD TDB
2 TBD TBD
4 TBD TBD
8 TBD TBD
Xilinx Artix 7 1 TBD TBD
2 TBD TBD
4 TBD TBD
8 TBD TBD
Xilinx Kintex 7 1 TBD TBD
2 TBD TBD
4 TBD TBD
8 TBD TBD
Xilinx Virtex 7 1 TBD TBD
2 TBD TBD
4 TBD TBD
8 TBD TBD

Files

Name Description
axi_jesd204_rx.v Verilog source for the peripheral.
axi_jesd204_rx_ip.tcl TCL script to generate the Vivado IP-integrator project for the peripheral.

Block Diagram

axi_jesd204_rx block diagram

Synthesis Configuration Parameters

Name Description Default
ID Instance identification number. 0
NUM_LANES Maximum number of lanes supported by the peripheral. 1
NUM_LINKS Maximum number of links supported by the peripheral. 1

Signal and Interface Pins

Name Type Description
s_axi_aclk Clock All S_AXI signals and irq are synchronous to this clock.
s_axi_aresetn Synchronous active low reset Resets the internal state of the peripheral.
S_AXI AXI4-Lite bus slave Memory mapped AXI-lite bus that provides access to modules register map.
irq Level-High Interrupt Interrupt output of the module. Is asserted when at least one of the modules interrupt is pending and enabled.
device_clk Clock Device clock for the JESD204B interface. Must be line clock / 40 for correct operation.
RX_DATA AXI4-Streaming interface Received data.
sync[m-1:0] Output JESD204B SYNC~ (or SYNC_N) signals. (0 <= m < NUM_LINKS)
sysref Input JESD204B SYSREF signal.
RX_PHYn JESD204B receive PHY interface n-th lane of the JESD204B interface (0 <= n < NUM_LANES).
phy_en_char_align Output Enable transceiver character alignment.
phy_ready Input Transceiver status.

Register Map

Address Name Type Reset Value Description
0x000 VERSION RO 0x00010061 Version of the peripheral. Follows semantic versioning. Current version 1.00.a.
[31:16] VERSION_MAJOR RO 0x0001
[15:8] VERSION_MINOR RO 0x00
[7:0] VERSION_PATCH RO 0x61
0x004 PERIPHERAL_ID RO 0x???????? Value of the ID configuration parameter.
0x008 SCRATCH RW 0x00000000 Scratch register.
0x00c IDENTIFICATION RO 0x32303454 Peripheral identification ('2', '0', '4', 'T').
0x010 SYNTH_NUM_LANES RO 0x???????? Number of supported lanes.
0x014 SYNTH_DATA_PATH_WIDTH RO 0x00000002 Internal data path width in octets.
0x018 SYNTH_REG_1 RO 0x???????? Core description register.
[31:8] Reserved RO 0x0000
[ 7:0] NUM_LINKS RO 0x?? Maximum supported links
0x040 SYNTH_ELASTIC_BUFFER_SIZE RO 0x00000100 Elastic buffer size in octets.
0x080 IRQ_ENABLE RW 0x00000000 Interrupt enable.
0x084 IRQ_PENDING RW1C-V 0x00000000 Pending and enabled interrupts.
0x088 IRQ_SOURCE RW1C-V 0x00000000 Pending interrupts.
0x0c0 LINK_DISABLE RW 0x00000001 JESD204B link disable.
[31:1] Reserved RO 0x00
[0] LINK_DISABLE RW 0x1 0 = Enable link, 1 = Disable link.
0x0c4 LINK_STATE RW-V 0x00000001 JESD204B link state.
[31:2] Reserved RO 0x00
[1] EXTERNAL_RESET RO 0x? 0 = External reset de-asserted, 1 = External reset asserted.
[0] LINK_STATE RO 0x1 0 = Link enabled, 1 = Link disabled.
0x0c8 LINK_CLK_FREQ RO-V 0x???????? Ratio of the device_clk frequency relative to the s_axi_aclk. Format is 16.16.
0x100 SYSREF_CONF RW 0x00000000 SYSREF configuration
[31:1] Reserved RO 0x00
[0] SYSREF_DISABLE RW 0x0 Enable/Disable SYSREF handling.
0x104 SYSREF_LMFC_OFFSET RW 0x00000000 SYSREF LMFC offset
[31:10] Reserved RO 0x00
[9:0] SYSREF_LMFC_OFFSET RW 0x00 Offset between SYSREF event and internal LMFC event in octets.
0x108 SYSREF_STATUS RW1C-V 0x00000000 SYSREF status
[31:2] Reserved RO 0x00
[1] SYSREF_ALIGNMENT_ERROR RW1C-V 0x0 Indicates that an external SYSREF event has been observed that was unaligned to a previously observed event.
[0] SYSREF_DETECTED RW1C-V 0x0 Indicates that an external SYSREF event has been observed.
0x200 LANES_DISABLE RW 0x00000000 Enabled/Disabled lanes.
[n] LANE_DISABLEn RW 0x0 Enable/Disable n-th lane (0 = enabled, 1 = disabled).
[1] LANE_DISABLE1 RW 0x0 Enable/Disable second lane (0 = enabled, 1 = disabled).
[0] LANE_DISABLE0 RW 0x0 Enable/Disable first lane (0 = enabled, 1 = disabled).
0x210 LINK_CONF0 RW 0x00000003 JESD204B link configuration.
[31:19] Reserved RO 0x00
[18:16] OCTETS_PER_FRAME RW 0x00 Number of octets per frame - 1 (F).
[15:8] Reserved RO 0x00
[7:0] OCTETS_PER_MULTIFRAME RW 0x03 Number of octets per multi-frame - 1 (K x F).
0x214 LINK_CONF1 RW 0x00000000 JESD204B link configuration.
[31:2] Reserved RO 0x0
[1] CHAR_REPLACEMENT_DISABLE RW 0x0 Enable/Disable user data alignment character replacement (0 = enabled, 1 = disabled).
[0] DESCRAMBLER_DISABLE RW 0x0 Enable/Disable user data descrambling (0 = enabled, 1 = disabled).
0x218 MULTI_LINK_DISABLE RW 0x00000000 Enable/Disable links in case of a multi-link architecture.
[n] LINK_DISABLEn RW 0x0 Enable/Disable n-th link (0 = enabled, 1 = disabled).
[1] LINK_DISABLE1 RW 0x0 Enable/Disable second link (0 = enabled, 1 = disabled).
[0] LINK_DISABLE0 RW 0x0 Enable/Disable first link (0 = enabled, 1 = disabled).
0x240 LINK_CONF2 RW 0x00000000 JESD204B link configuration.
[31:17] Reserved RO 0x0
[16] BUFFER_EARLY_RELEASE RW 0x0 Elastic buffer release point.
[15:12] Reserved RO 0x0
[11:0] BUFFER_DEALY RW 0x0 Buffer release opportunity offset from LMFC.
0x244 LINK_CONF3 RW 0x00000000 JESD204B error statistics configuration.
[31:11] Reserved RO 0x0
[10] MASK_UNEXPECTEDK RW 0x0 If set, unexpected k errors are not counted
[9] MASK_NOTINTABLE RW 0x0 If set, not in table errors are not counted
[8] MASK_DISPERR RW 0x0 If set, disparity errors are not counted
[7:1] Reserved RO 0x0
[0] RESET_COUNTER RW 0x0 If set, resets the error counter
0x280 LINK_STATUS RO-V 0x00000000 JESD204B link status.
[31:2] Reserved RO 0x00
[1:0] STATUS_STATE RO-V 0x00 State of the link state machine. (0 = RESET, 1 = WAIT_FOR_PHY, 2 = CGS, 3 = SYNCHRONIZED)
0x300 + (0x20 * n) LANEn_STATUS RO-V 0x00000000
[31:6] Reserved RO 0x0
[5] ILAS_READY RO-V 0x0 ILAS configuration data received.
[4] IFS_READY RO-V 0x0 Frame synchronization state.
[3:2] Reserved RO 0x0
[1:0] CGS_STATE RO-V 0x0 State of the lane code group synchronization. (0 = INIT, 1 = CHECK, 2 = DATA)
0x304 + (0x20 * n) LANEn_LATENCY RO-V 0x00000000
[31:14] Reserved RO 0x0
[13:0] LATENCY RO-V 0x0 Lane latency in octets.
0x308 + (0x20 * n) LANEn_ERROR_STATISTICS RO 0x00000000
[31:0] ERROR_REGISTER RO 0x0 This register shows the number of total errors for this lane. Errors counted depend on the configuration in LINK_CONF3. It must always be manually reset.
0x310 + (0x20 * n) LANEn_ILAS0 RW 0x00000000 ILAS config data for the n-th lane.
[31:28] Reserved RO 0x0
[27:24] BID RW 0x0 BID (Bank ID) field of the ILAS config sequence.
[23:16] DID RW 0x00 DID (Device ID) field of the ILAS config sequence.
[15:0] Reserved RO 0x0000
0x314 + (0x20 * n) LANEn_ILAS1 RW 0x00000000 ILAS config data for the n-th lane.
[31:29] Reserved RO 0x00
[28:24] K RW 0x00 K (Frames per multi-frame) field of the ILAS config sequence.
[23:16] F RW 0x00 F (Octets per frame) field of the ILAS config sequence.
[15] SCR RW 0x00 SCR (Scrambling enabled) field of the ILAS config sequence.
[14:13] Reserved RO 0x0
[12:8] L RW 0x00 L (Number of lanes) field of the ILAS config sequence.
[7:5] Reserved RO 0x0
[4:0] LID RW 0x00 LID (Lane ID) field of the ILAS config sequence
0x318 + (0x20 * n) LANEn_ILAS2 RW 0x00000000 ILAS config data for the n-th lane.
[31:29] JESDV RW 0x0 JESDV (JESD204 version) field of the ILAS config sequence.
[28:24] S RW 0x00 S (Samples per frame) field of the ILAS config sequence.
[23:21] SUBCLASSV RW 0x0 SUBCLASSV (JESD204B subclass) field of the ILAS config sequence.
[20:16] NP RW 0x00 N' (Total number of bits per sample) field of the ILAS config sequence.
[15:14] CS RW 0x0 CS (Control bits per sample) field of the ILAS config sequence.
[13] Reserved RO 0x0
[12:8] N RW 0x00 N (Converter resolution) field of the ILAS config sequence.
[7:0] M RW 0x00 M (Number of converters) field of the ILAS config sequence.
0x31C + (0x20 * n) LANEn_ILAS3 RW 0x00000000 ILAS config data for the n-th lane.
[31:24] FCHK RW 0x00 FCHK (Checksum) field of the ILAS config sequence.
[23:8] Reserved RO 0x0
[7] HD RW 0x0 HD (High-density) field of the ILAS config sequence.
[6:5] Reserved RO 0x0
[4:0] CF RO 0x00 CF (control words per frame) field of the ILAS config sequence.
Access Type Name Description
RO Read-only Reads will return the current register value. Writes have no effect.
RW Read-write Reads will return the current register value. Writes will change the current register value.
RW1C Write-1-to-clear Reads will return the current register value. Writing the register will clear those bits of the register which were set to 1 in the value written.
V Volatile The V suffix indicates that the register is volatile and its content might change without software interaction. The value of a non-volatile register will not change without an explicit write done by software.

Theory of Operation

The JESD204B receive peripheral consists of two main components. The register map and the link processor. Both components are fully asynchronous and are clocked by independent clocks. The register map is in the s_axi_aclk clock domain, while the link processor is in the device_clk clock domain.

The register map is used to configure the operational parameters of the link processor as well as to query the current state of the link processor. The link processor itself is responsible for handling the JESD204B link layer protocol.

Interfaces and Signals

Register Map Configuration Interface

The register map configuration interface can be accessed through the AXI4-Lite S_AXI interface. The interface is synchronous to the s_axi_aclk. The s_axi_aresetn signal is used to reset the peripheral and should be asserted during system startup until the s_axi_aclk is active and stable. De-assertion of the reset signal should be synchronous to s_axi_aclk.

JESD204B Control Signals

The sync and sysref signals correspond to the SYNC~ and SYSREF signals of the JESD204B specification.

The sync signal is asserted by the peripheral during link initialization and must be connected to the corresponding JESD204B ADC converter devices on the same link.

The sysref signal is generated externally and is optional. It is only required to achieve deterministic latency in subclass 1 mode operation. If the sysref signal is not connected software needs to configure the peripheral accordingly to indicate this.

When the sysref signal is used, in order to ensure correct operation, it is important that setup and hold of the external signal relative to the device_clk signal are met. Otherwise, deterministic latency cannot be guaranteed.

Transceiver Interface (RX_PHYn)

For each lane, the peripheral has one corresponding RX_PHY interface. These interfaces accept the physical layer data from the downstream physical layer transceiver peripheral.

The physical layer is responsible for clock recovery, character alignment, de-serialization as well an 8b10b decoding.

User Data Interface (RX_DATA)

User data is provided on the AXI4-Stream RX_DATA interface. The interface is a reduced AXI4-Stream interface and only features the TVALID flow control signal, but not the TREADY flow control signal. The behavior of the interface is as if the TREADY signal was always asserted. This means as soon as rx_valid is asserted a continuous stream of user data must be accepted from rx_data.

After reset and during link initialization the rx_valid signal is de-asserted. As soon as the User Data Phase is entered the rx_valid will be asserted to indicate that the peripheral is now providing and the processed data at the rx_data signal. The rx_valid signal stays asserted until the link is either deactivated or re-initialized.

Typically the RX_DATA interface is connected to a JESD204B transport layer peripheral that de-frames the data and passes it to the application layer. The internal data path width of the peripheral is four, this means that four octets per lane are processed in parallel. When in the user data phase the peripheral provides four octets for each lane in each beat.

This means that RX_DATA interface is 32 * NUM_LANES bits wide. With each block of consecutive 32 bits corresponding to one lane. The lowest 32 bits correspond to the first lane, while the highest 32 bits correspond to the last lane. Each lane specific 32-bit block corresponds to four octets each 8 bits wide. The temporal ordering of the octets is from LSB to MSB, this means the octet placed in the lowest 8 bits was received first, the octet placed in the highest 8 bits was received last.

Data corresponding to lanes that have been disabled should be ignored and their value is undefined.

Configuration Interface

The peripheral features a register map configuration interface that can be accessed through the AXI4-Lite S_AXI port. The register map can be used to configure the peripherals operational parameters, query the current status of the device and query the features supported by the device.

Peripheral Identification and HDL Synthesis Settings

The peripheral contains multiple registers that allow the identification of the peripheral as well as the discovery of features that were configured at HDL synthesis time. Apart from the SCRATCH register all registers in this section are read-only and write access to them will be ignored.

The VERSION (0x000) register contains the version of the peripheral. The version determines the register map layout and general features supported by the peripheral. The version number follows semantic versioning. Increments in the major number indicate backward incompatible changes, increments in the minor number indicate backward compatible changes, patch letter increments indicate bug fix.

The PERIPHERAL_ID (0x004) register contains the value of the ID HDL configuration parameter that was set during synthesis. Its primary function is to allow to distinguish between multiple instances of the peripheral in the same design.

The SCRATCH (0x008) register is a general purpose 32-bit register that can be set to an arbitrary values. Reading the register will yield the value previously written (The value will be cleared when the peripheral is reset). Its content does not affect the operation of the peripheral. It can be used by software to test whether the register map is accessible or store custom peripheral associated data.

The IDENTIFICATION (0x00c) register contains the value of “204R”. This value is unique to this type of peripheral and can be used to ensure that the peripheral exists at the expected location in the memory mapped IO register space.

The SYNTH_NUM_LANES (0x010) register contains the value of the NUM_LANES HDL configuration parameter that was set during synthesis. It corresponds to the maximum of lanes supported by the peripheral. Possible values are between 1 and 32.

The SYNTH_DATA_PATH_WIDTH (0x014) register contains the value of the internal data path width per lane in octets. This is how many octets are processed in parallel on each lane and affects the restrictions of possible values for certain runtime configuration registers. The value is encoded as the log2() of the data path width. Possible values are:

  • 1: Internal data path width is 2
  • 2: Internal data path width is 4
  • 3: Internal data path width is 8

The SYNTH_ELASTIC_BUFFER_SIZE (0x040) register describes the maximum amount of octets that the elastic buffer can hold. This puts a limit on the maximum local-multi-frame-clock (LMFC) period (subclass 1) as well as the maximum skew between individual lanes (subclass 0). Both must be less than the elastic buffer size.

Interrupt Handling

Interrupt processing is handled by three closely related registers. All three registers follow the same layout, each bit in the register corresponds to one particular interrupt.

When an interrupt event occurs it is recorded in the IRQ_SOURCE (0x088) register. For a recorded interrupt event the corresponding bit is set to 1. If an interrupt event occurs while the bit is already set to 1 it will stay set to 1.

The IRQ_ENABLE (0x080) register controls how recorded interrupt events propagate. An interrupt is considered to be enabled if the corresponding bit in the IRQ_ENABLE register is set to 1, it is considered to be disabled if the bit is set to 0.

Disabling an interrupt will not prevent it from being recorded, but only its propagation. This means if an interrupt event was previously recorded while the interrupt was disabled and the interrupt is being enabled the interrupt event will then propagate.

An interrupt event that has been recorded and is enabled propagates to the IRQ_PENDING (0x084) register. The corresponding bit for such an interrupt will read as 1. Disabled or interrupts for which no events have been recorded will read as 0. Also if at least one interrupt has been recorded and is enabled the external irq signal will be asserted to signal the IRQ event to the upstream IRQ controller.

A recorded interrupt event can be cleared (or acknowledged) by writing a 1 to the corresponding bit to either the IRQ_SOURCE or IRQ_PENDING register. It is possible to clear multiple interrupt events at the same time by setting multiple bits in a single write operation.

For more details regarding interrupt operation see the interrupts section of this document.

The LINK_DISABLE (0x0c0) register is used to control the link state and switch between enabled and disabled. While the link is disabled its state machine will remain in reset and it will not react to any external event like the SYSREF or SYNC~ signals.

Writing a 0 to the LINK_DISABLE register will enable the link. While the link state is changing from disabled to enabled it will go through a short initialization procedure, which will take a few clock cycles. To check whether the initialization procedure has completed and the link is fully operational the LINK_STATE (0x0c4) register can be checked. The LINK_STATE ([0]) bit will contain a 1 when the link is fully enabled and will contain a 0 while it is disabled or going through the initialization procedure.

Writing a 1 to the LINK_DISABLE register will immediately disable the link.

The EXTERNAL_RESET ([1]) bit in the LINK_STATE register indicates whether the external link reset signal is asserted (1) or de-asserted (0). When the external link reset is asserted the link is disabled regardless of the setting of LINK_DISABLE. The external link reset is controlled by the fabric and might be asserted if the link clock is not stable yet.

A multi-link is a link where multiple converter devices are connected to a single logic device (FPGA). All links involved in a multi-link are synchronous and established at the same time. For an RX link, this means that the SYNC~ signal needs to be propagated from the FPGA to each converter.

The MULTI_LINK_DISABLE register allows activating or deactivating each SYNC~ lines independently. This is useful when depending on the use case profile some converter devices are supposed to be disabled.

The link configuration registers control certain aspects of the runtime behavior of the peripheral. Since the JESD204B standard does now allow changes to link configuration while the link is active the link configuration registers can only be modified while the link is disabled. As soon as it is enabled the configuration registers turn read-only and any writes to them will be ignored.

The LANES_DISABLE (0x200) register allows to disable individual lanes. Each bit in the register corresponds to a particular lane and indicates whether that lane is enabled or disabled. Bit 0 corresponds to the first lane, bit 1 to the second lane and so on. A value of 0 for a specific bit means the corresponding lane is enabled, a value of 1 means the lane is disabled. A disabled lane will not receive any data when the link is otherwise active. By default, all lanes are enabled.

The LINK_CONF0 register configures the octets-per-frame and frames-per-multi-frame settings of the link. The OCTETS_PER_FRAME ([18:16]) field should be set to the number of octets-per-frame minus 1 (F - 1). The OCTETS_PER_MULTIFRAME ([7:0]) field should be set to the number of octets-per-frame multiplied by the number of frames-per-multi-frame minus 1 (FxK - 1). For correct operation FxK must be a multiple of 4.

The LINK_CONF1 register allows disabling optional link level processing stages. The DESCRAMBLER_DISABLE ([0]) bit controls whether descrambling of the received user data is enabled or disabled. A value of 0 enables descrambling and a value of 1 disables it. The CHAR_REPLACEMENT_DISABLE ([1]) bit controls whether alignment character replacement is performed or not. A value of 0 enables character replacement and a value of 1 disables it. If character replacement is disabled and an alignment character is received (/F/ or /A/) a unexpected K-character error is raised.

For correct operation, character replacement must be disabled when descrambling is disabled otherwise undefined behavior might occur.

Both the transmitter as well as receiver device on the JESD204B link need to be configured with the same settings for scrambling/descrambling and character replacement for correct operation.

The LINK_CONF2 register controls the behavior of elastic buffer. The BUFFER_EARLY_RELEASE ([16]) bit configures when the data is released from the elastic buffer to the RX_DATA port. If the bit is set to 0 the data will be released at the earliest configured release point after all lanes are ready. When the bit is set to 1 the data will be released as soon as all lanes are ready. The former gives deterministic latency and is required for subclass 1 operation, the later gives minimum latency.

The BUFFER_DELAY ([11:0]) field allows to configure the buffer release opportunity point relative to the local-multi frame-clock (LMFC). A setting of 0 indicates that the release opportunity is aligned to the LMFC edge. A setting of X indicates that it trails the LMFC edge by X octets.

BUFFER_DEALY timing

The BUFFER_DELAY field must be set to a multiple of 4. Writing a value that is not a multiple of 4 will be rounded down to the next multiple of 4. For correct operation, the BUFFER_DELAY field must also be set to a value smaller than the number of octets per multi-frame (FxK).

This mechanism can be used to reduce overall latency while still maintaining deterministic latency if the maximum link latency (overall valid PVT settings) is known.

SYSREF Handling

The external SYSREF signal is used to align the internal local multiframe clocks (LMFC) between multiple devices on the same link.

The SYSREF_CONF (0x100) register allows to configure the behavior of the SYSREF capture circuitry. Setting the SYSREF_DISABLE ([0]) bit to 1 disables the SYSREF handling. All external SYSREF events are ignored and the LMFC is generated internally. For Subclass 1 operation SYSREF handling should be enabled and for Subclass 0 operation it should be disabled.

The SYSREF_LMFC_OFFSET (0x104) register allows to modify the offset between the SYSREF rising edge and the rising edge of the LMFC.

For optimal operation it is recommended that all device on a JESD204 link should be configured in a way so that the total offset between

The value of the SYSREF_LMFC_OFFSET register must be set to a value smaller than the configured number of octets-per-multiframe (OCTETS_PER_MULTIFRAME), otherwise undefined behavior might occur.

The SYSREF_STATUS (0x108) register allows to monitor the status of the SYSREF signals. SYSREF_DETECTED ([0]) bit indicates that the peripheral as observed a SYSREF event. The SYSREF_ALIGNMENT_ERROR ([1]) bit indicates that a SYSREF event has been observed which was unaligned, in regards to the LMFC period, to a previously recorded SYSREF event.

All bits in the SYSREF_STATUS register are write-to-clear. All bits will also be cleared when the link is disabled.

Note that the SYSREF_STATUS register will not record any events if SYSREF operation is disabled or the JESD204 link is disabled.

All link status registers are read-only. While the link is disabled some of the link status registers might contain bogus values. Their content should be ignored until the link is fully enabled.

The STATUS_STATE ([1:0]) field of the LINK_STATUS (0x280) register indicates the state of the link state machine.

Possible values are:

  • RESET (0x0): The link is currently disabled
  • WAIT FOR PHY (0x1): The controller waits for the PHY level component to be ready
  • CGS (0x2): The controller is waiting for one or more lanes to complete the CGS phase
  • DATA (0x3): All lanes are om the data phase and the link is properly established

The state of each individual lane can be queried from the lane status registers.

Lane Status

Each lane has a independent status register (LANEn_STATUS (0x300)) that indicates the current state of the lane.

The CGS_STATE ([1:0]) indicates the current state of the lane code group synchronization:

  • INIT (0x0): Lane is not synchronized.
  • CHECK (0x1): Lane is in the process of synchronizing, at least some /K/ synchronization characters have been observed.
  • DATA (0x2): Lane is synchronized and ready to receive data.

The IFS_READY ([4]) bit indicates that initial frame synchronization has completed for the lane and the lane is receiving either ILAS data or user data.

The LANEn_LATENCY (0x304) register holds the duration in octets between when the SYNC~ signal was de-asserted and when the frame synchronization for this particular lane has completed. The LANEn_LATENCY register only holds valid data if the IFS_READY bit of the LANEn_STATUS register is set.

ILAS Configuration Data

If the JESD204B transmitter emits an initial lane alignment sequence (ILAS) the configuration data embedded in the second multi-frame of the ILA sequence is captured by the peripheral and stored in a set of four per-lane registers (LANEn_ILAS0, LANEn_ILAS1, LANEn_ILAS2 and LANEn_ILAS3). ILAS_READY ([5]) bit in the corresponding LANEn_STATUS register indicates whether the ILAS configuration data has been captured for a specific lane. The data in the LANEn_ILASx registers is only valid when that bit is asserted.

The received ILAS configuration data can be used to verify that the transmitter device is using the expected configuration and that the lane and device mapping is correct.

Clock Monitor

The LINK_CLK_FREQ (0x0c8) register allows to determine the clock rate of the device clock (device_clk) relative to the AXI interface clock (s_axi_aclk). This can be used to verify that the device clock is running at the expected rate.

The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock this corresponds to a resolution of 1.523kHz per LSB. A raw value of 0 indicates that the link clock is currently not active.

Interrupts

The peripheral can be in one of four main operating phases: RESET, WAIT FOR PHY, CGS, or DATA. Upon reset the peripheral starts in the RESET phase. The WAIT FOR PHY and CGS phases are used during the initialization of the JESD204B link. The DATA phase is used during normal operation when user data is received across the JESD204B link.

RESET phase

The RESET phase is the default state entered during reset. While disabled the peripheral will stay in the RESET phase. When enabled the peripheral will transition from the RESET phase to the WAIT FOR PHY phase.

If at any point the peripheral is disabled it will automatically transition back to the RESET state.

Lanes that have been disabled in the register map configuration interface will behave as if the link was in the RESET state regardless of the actual state.

WAIT FOR PHY phase

During the WAIT FOR PHY phase the peripheral will wait for all PHY controllers for all enabled lanes to be ready for operation. Once this condition is satisfied the controlled will transition to the CGS phase.

CGS phase

During the CGS phase the peripheral will assert the external ~SYNC signal and expects the connected JESD204 transmitter to send /K/ characters.

Each lane will independently the incoming data stream for /K/ characters and adjust its state machine according to the received characters.

Once all enabled lanes have entered the DATA state the link state will transition from the CGS phase to the DATA phase.

DATA phase

The DATA phase is the main operating mode of the peripheral. In this phase it will transmit transport layer data at the RX_DATA port. When the peripheral enters the DATA phase the valid signal of the RX_DATA interface will be asserted to indicate that transport layer data is now available.

By default the data received on each lane will is descrambled. Descrambling can optionally be disabled via the register map configuration interface. Descrambling is enabled or disabled for all lanes equally.

Scrambling reduces data-dependent effects, which can affect both the analog performance of the data converter as well as the bit-error rate of JESD204B serial link, therefore it is highly recommended to enable scrambling for the link.

The peripheral also performs per-lane alignment character monitoring. When alignment character replacement is enabled the JESD204B transmitter replaces under certain predictable conditions (i.e. the receiver can recover the replaced character) the last octet in a frame or multi-frame. Replaced characters at the end of a frame, that is also the end of a multi-frame, are replaced by the /A/ character. Replaced characters at the end of a frame, that is not the end of a multi-frame, are replaced by the /F/ character. If a alignment character is received the peripheral checks that the it is in the expected position, either the end of a frame or the end of a multi-frame, and reports an error if a lane has become misaligned. This allows to detect alignment errors and allows the application to re-initialize the link.

Alignment character monitoring can optionally be disabled via the register map configuration interface. Alignment character monitoring is enabled or disabled for all lanes equally. If alignment character monitoring is disabled no errors are reported when a misaligned alignment character is received.

Data on the RX_DATA port corresponding to a disabled lanes are undefined and should be ignored.

Diagnostics

Software Support

To ensure correct operation it is highly recommended to use the Analog Devices provided JESD204B software packages for interfacing the peripheral. Analog Devices is not able to provide support in case issues arise from using custom low-level software for interfacing the peripheral.

Restrictions

During the design of the peripheral the deliberate decision was made to support only a subset of the features mandated by the JESD204B standard for receiver logic devices. The reasoning here is that the peripheral has been designed to interface to Analog Devices JESD204B ADC converter devices and features that are either not required or not supported by those converter devices would otherwise lie dormant in peripheral and never be used. Instead the decision was made to not implement those unneeded features even when the JESD204B standard requires them for general purpose JESD204B receiver logic devices. As Analog Devices ADC converter devices with new requirements are released the peripheral will be adjusted accordingly.

This approach allows for a leaner design using less resources, allowing for lower pipeline latency and a higher maximum device clock frequency.

The following lists where the peripheral deviates from the standard:

  • No subclass 2 support. JESD204B subclass 2 has due to its implementation details restricted applicability and is seldom a viable option for a modern high-speed data converter system. To achieve deterministic latency it is recommend to use subclass 1 mode.
  • Reduced number of octets-per-frame settings. The JESD204B standard allows for any value between 1 and 256 to be used for the number of octets-per-frame. The following values are supported by the peripheral: 1, 2, 4 and 8.
  • Reduced number of frames-per-multi-frame settings. The following values are supported by the peripheral: 1-32, with the additional requirement that F*K is a multiple of 4. In addition F*K needs to be in the range of 4-256.
  • No support for alignment character replacement when scrambling is disabled.

Supported Devices

Technical Support

Analog Devices will provide limited online support for anyone using the core with Analog Devices components (ADC, DAC, Clock, etc) via the EngineerZone under the GPL license. If you would like deterministic support when using this core with an ADI component, please investigate a commercial license. Using a non-ADI JESD204 device with this core is possible under the GPL, but Analog Devices will not help with issues you may encounter.

More Information

resources/fpga/peripherals/jesd204/axi_jesd204_rx.txt · Last modified: 26 Apr 2018 16:22 by AdrianC