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The JESD204, JESD204A and the JESD204B data converter serial interface standard was created through the JEDEC committee to standardize and reduce the number of data inputs/outputs between high-speed data converters and other devices, such as FPGAs (field-programmable gate arrays). Fewer interconnects simplifies layout and allows smaller form factor realization without impacting overall system performance. These attributes are important to address the system size and cost constraints of a range of high speed ADC applications, including wireless infrastructure (GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA) transceiver architectures, software-defined radios, portable instrumentation, medical ultrasound equipment, and Mil/Aero applications such as radar and secure communications. Analog Devices is an original participating member of the JEDEC JESD204 standards committee and we have concurrently developed compliant data converter technology and tools, and a comprehensive product roadmap to fully enable our customers to take advantage of this significant interfacing breakthrough.
Analog Devices supplies a full-stack supporting JESD204B which provides a fully integrated system level experience. This solution includes
When customers and partners download software from github, or e-mail downloaded software to someone, they are obligated to comply to the terms and conditions of the Software License Agreement. The core is released under two difference licenses. You may choose either:
There is only one core, the only difference is the license and support. If you have a question about the license: you can email jesd204 [dash] licensing [at] analog [dot] com.
The JESD204B standard defines multiple layers, each layer being responsible for a particular function. The Analog Devices JESD204B HDL solution follows the standard here and defines 4 layers. Physical layer, link layer, transport layer and application layer. For the first three layers Analog Devices provides standard components that can be linked up to provide a full JESD204B protocol processing chain.
Depending on the FPGA and converter combinations that are being interfaced different components can be chosen for the physical and transport layer. The FPGA defines which physical layer component should be used and the interfaced converter defines which transport layer component should be used.
The link layer component is selected based on the direction of the JESD204B link.
The application layer is user defined and can be used to implement application specific signal processing.
Physical layer peripherals are responsible for interfacing and configuring the high-speed serial transceivers.
Link layer peripherals are responsible for JESD204B protocol handling, including scrambling/descrambling, lane alignment, character replacement and alignment monitoring.
Transport layer peripherals are responsible for converter specific data framing and de-framing.
Interfaces are a well-defined collection of wires that are used to communicate between components. The following interfaces are used to connect components of the HDL JESD204B processing stack.