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This version (12 Feb 2019 10:07) was approved by AdrianC.The Previously approved version (30 Jan 2019 09:45) is available.Diff

AXI_ADXCVR

The AXI_ADXCVR is a transceiver core used to implement a JESD204B device link. The same core is used in both Altera and Xilinx devices. It replaces the AXI_JESD_GT and AXI_JESD_XCVR cores used in previous implementations. The core itself does NOT instantiate any transceiver primitives, but is expected to be interfaced with the UTIL_ADXCVR core. A single AXI_ADXCVR core must interface with a JESD204B device. The pair may have multiple links per interface, but all the interface parameters must be identical. The core allows transceiver sharing across asymmetrical and multiple links across the receive and transmit pairs.

Features

  • Supports Altera and Xilinx devices.
  • A simple SW interface, software is only expected to bring the core out of reset and monitor the status. The transceiver initialization sequence walk through is fully handled by the HDL.
  • Transceiver sharing is supported with the Avalon Interface active (Altera).
  • Reconfiguration access allows broadcast, SW may choose to see the link as a single primitive (Xilinx).
  • Statistical eye scan (Xilinx) and 2D EyeQ (Altera) fully implemented in HDL.
  • No JESD204B specific functionality, the SYSREF/SYNC functionality featured in AXI_JESD_GT cores are removed.
  • Supports up to 16 transceiver lanes per link.

Altera Devices

Xilinx Devices

In Xilinx Devices, the core configures itself to be interfaced with the GT variant supported by the UTIL_ADXCVR core. All the transceiver primitives are configured and programmed identical.

Parameters

Name Description Default Value
ID Instance identification number, if more than one instance is used. 0
NUM_OF_LANES The number of lanes (primitives) used in this link. 8
XCVR_TYPE Define the current GT type, GTXE2(0), GTHE3(1), GTHE4(2). 0
TX_OR_RX_N If set (0x1), configures the link in transmit mode, otherwise receive. 0
QPLL_ENABLE If set (0x1), configures the link to use QPLL on QUAD basis. If multiple links are sharing the same transceiver, only one of them may enable the QPLL. 1

Interface

Interface Pin Type Description
axi_clk axi_clk Input The CPU clock (assumed to be 100MHz), must be same as the DRP clock.
axi_aresetn axi_aresetn Input The CPU reset (internally used asynchronous to the axi_clk).
up_status up_status Output If set, indicates that the link is up and active. The same information is read on the register bit (see below). This signal may be connected to the JESD204B IP reset done input.
s_axi Slave-AXI IO The programmable interface, must be connected to a CPU master.
m_axi Master-AXI IO The Eye-Scan DMA interface, must be connected to a memory slave. This interface is available only if parameter TX_OR_RX_N is set to 0x0.
up_cm_* Common-DRP IO The common DRP interface, must be connected to the equivalent DRP ports of UTIL_ADXCVR. This is a QUAD interface, shared by four transceiver lanes. This interface is available only if parameter QPLL_ENABLE is set to 0x1.
up_ch_* Channel-DRP IO The channel DRP interface, must be connected to the equivalent DRP ports of UTIL_ADXCVR. This is a channel interface, one per each transceiver lane.
up_es_* Eye-Scan-DRP IO The Eye-Scan DRP interface, must be connected to the equivalent DRP ports of UTIL_ADXCVR. This is a channel interface, one per each transceiver lane. This interface is available only if parameter TX_OR_RX_N is set to 0x0.

Register Map

Address Bits Name Type Description
DWORD BYTE
0x0000 0x0000 REG_VERSION Version Register
[31:0] VERSION[31:0] RO Version number.
0x0001 0x0004 REG_ID Instance Identification Register
[31:0] ID[31:0] RO Instance identifier number.
0x0002 0x0008 REG_SCRATCH Scratch (GP R/W) Register
[31:0] SCRATCH[31:0] RW Scratch register.
0x0004 0x0010 REG_RESETN Reset Control Register
[0] RESETN RW If clear, link is held in reset, set this bit to 0x1 to activate link. Note that the reference clock and DRP clock must be active before setting this bit.
0x0005 0x0014 REG_STATUS Status Reporting Register
[0] STATUS RO After setting the RESETN bit above, wait for this bit to set. If set, indicates successful link activation.
0x0008 0x0020 REG_CONTROL Transceiver Control Register
[12] LPM_DFE_N RW Transceiver primitive control, refer Xilinx documentation.
[10:8] RATE[2:0] RW Transceiver primitive control, refer Xilinx documentation.
[5:4] SYSCLK_SEL[1:0] RW Transceiver primitive control, refer Xilinx documentation. It controls the [RX/TX]SYSCLKSEL for 7 Series devices and [RX/TX]PLLCLKSEL and also[RX/TX]SYSCLKSEL for Ultrascale(+) devices.
[2:0] OUTCLK_SEL[2:0] RW Transceiver primitive control, refer Xilinx documentation.
0x0010 0x0040 REG_CM_SEL Transceiver Access Register
[7:0] CM_SEL[7:0] RW Transceiver common-DRP sel, set to 0xff for broadcast.
0x0011 0x0044 REG_CM_CONTROL Transceiver Access Register
[28] CM_WR RW Transceiver common-DRP sel, set to 0x1 for write, 0x0 for read.
[27:16] CM_ADDR[11:0] RW Transceiver common-DRP read/write address.
[15:0] CM_WDATA[15:0] RW Transceiver common-DRP write data.
0x0012 0x0048 REG_CM_STATUS Transceiver Access Register
[16] CM_BUSY RO Transceiver common-DRP access busy (0x1) or idle (0x0).
[15:0] CM_RDATA[15:0] RW Transceiver common-DRP read data.
0x0018 0x0060 REG_CH_SEL Transceiver Access Register
[7:0] CH_SEL[7:0] RW Transceiver channel-DRP sel, set to 0xff for broadcast.
0x0019 0x0064 REG_CH_CONTROL Transceiver Access Register
[28] CH_WR RW Transceiver channel-DRP sel, set to 0x1 for write, 0x0 for read.
[27:16] CH_ADDR[11:0] RW Transceiver channel-DRP read/write address.
[15:0] CH_WDATA[15:0] RW Transceiver channel-DRP write data.
0x001a 0x0068 REG_CH_STATUS Transceiver Access Register
[16] CH_BUSY RO Transceiver channel-DRP access busy (0x1) or idle (0x0).
[15:0] CH_RDATA[15:0] RW Transceiver channel-DRP read data.
0x0020 0x0080 REG_ES_SEL Transceiver Access Register
[7:0] ES_SEL[7:0] RW Transceiver eye-scan-DRP sel, set to 0xff for broadcast.
0x0028 0x00a0 REG_ES_REQ Transceiver eye-scan Request Register
[0] ES_REQ RW Transceiver eye-scan request, set this bit to initiate an eye-scan, this bit auto-clears when scan is complete.
0x0029 0x00a4 REG_ES_CONTROL_1 Transceiver eye-scan Control Register
[4:0] ES_PRESCALE[4:0] RW Transceiver eye-scan control, refer Xilinx documentation.
0x002a 0x00a8 REG_ES_CONTROL_2 Transceiver eye-scan Control Register
[25:24] ES_VOFFSET_RANGE[1:0] RW Transceiver eye-scan control, refer Xilinx documentation.
[23:16] ES_VOFFSET_STEP[7:0] RW Transceiver eye-scan control, refer Xilinx documentation.
[15:8] ES_VOFFSET_MAX[7:0] RW Transceiver eye-scan control, refer Xilinx documentation.
[7:0] ES_VOFFSET_MIN[7:0] RW Transceiver eye-scan control, refer Xilinx documentation.
0x002b 0x00ac REG_ES_CONTROL_3 Transceiver eye-scan Control Register
[27:16] ES_HOFFSET_MAX[11:0] RW Transceiver eye-scan control, refer Xilinx documentation.
[11:0] ES_HOFFSET_MIN[11:0] RW Transceiver eye-scan control, refer Xilinx documentation.
0x002c 0x00b0 REG_ES_CONTROL_4 Transceiver eye-scan Control Register
[11:0] ES_HOFFSET_STEP[11:0] RW Transceiver eye-scan control, refer Xilinx documentation.
0x002d 0x00b4 REG_ES_CONTROL_5 Transceiver eye-scan Control Register
[31:0] ES_STARTADDR[31:0] RW Transceiver eye-scan control, DMA start address (ES data is written to this memory address).
0x002e 0x00b8 REG_ES_STATUS Transceiver eye-scan Status Register
[0] ES_STATUS[0] RO If set, indicates an error in ES DMA.
0x0030 0x00c0 REG_TX_DIFFCTRL Transceiver primitive control, refer Xilinx documentation.
[31:0] REG_TX_DIFFCTRL[31:0] RW TX driver swing control.
0x0031 0x00c4 REG_TX_POSTCURSOR Transceiver primitive control, refer Xilinx documentation.
[31:0] REG_TX_POSTCURSOR[31:0] RW Transmiter post-cursor TX pre-emphasis control.
0x0032 0x00c8 REG_TX_PRECURSOR Transceiver primitive control, refer Xilinx documentation.
[31:0] REG_TX_PRECURSOR[31:0] RW Transmiter pre-cursor TX pre-emphasis control.

Software Guidelines

The system must have active DRP and reference clocks before any software access. The software is expected to write necessary control parameters to LPM_DFE_N, RATE, SYSCLK_SEL, OUTCLK_SEL register bits and then set RESETN bit to 0x1. After which monitor the STATUS bit to be set. There are no other requirements for initialization.

The DRP access is identical for common and channel interfaces. The SEL bits may be set to a specific transceiver lane or 0xff to broadcast. A write to the CONTROL register (bits WR, ADDR, WDATA) initiates DRP access in hardware. A read to this register has no effect. In order to write to the transceiver, set WR to 0x1 with the address. In order to read from the transceiver, set WR to 0x0 with the address. As soon as this register is written, the BUSY signal is set and is cleared only after the access is complete. The broadcast read is a logical OR of all the channels. After an access is started, do NOT interrupt the core for any reason (including setting RESETN to 0x0), allow the access to finish itself. Though the core itself is immune to a software abort, the transceiver may fail on further accesses and may require a system-wide reset.

The eye-scan feature also allows a SEL option and a broadcast has the effect of a combined mask. That is, the error counter will be zero ONLY if all the transceiver error counters are zero. To start eye-scan, set ES_REQ to 0x1 and wait for the same bit to self-clear. If eye-scan needs to be stopped, set the ES_REQ bit to 0x0.

More Information

resources/fpga/docs/axi_adxcvr.txt · Last modified: 12 Feb 2019 10:07 by AdrianC