This version (24 Apr 2023 09:37) was approved by Michael Hennerich.The Previously approved version (07 Jul 2022 08:45) is available.
Table of Contents
AD9081/AD9082 Virtex UltraScale+ VCU118 Quick Start Guide
This guide provides some quick instructions (still takes awhile to download, and set things up) on how to setup the AD9081-FMCA-EBZ or AD9082-FMCA-EBZ on the VCU118 platform.
Prerequisites
Required Hardware
- Xilinx VCU118 Rev 1.0 or later board
- AD9081-FMCA-EBZ or AD9082-FMCA-EBZ board.
- 2 x Micro-USB cable
- Ethernet cable
- Signal generator
- 4 way splitter (optional)
Required Software
- A Linux OS on a PC
- Xilinx Vivado 2019.1 or later
- UART terminal (e.g TeraTerm)
- IIO-Oscilloscope Download
Downloads (Pre-build Images for VCU118)
Example Device Trees
Board setup
The following rework is required:
- In order to avoid using an external clock source and fully rely on the HMC7044 clock chip, rotate the C6D/C4D caps in C5D/C3D position (Please note: In the latest version of the board, this is now the default configuration, so this configuration step might not be needed anymore)
- If LEDS V1P0_LED and VINT_LED are not on please depopulate R22M and populate R2M
Steps
1. Build the HDL project
Before building the hdl project setup your computer based on the following guide: Building HDL projects
git clone https://github.com/analogdevicesinc/hdl.git git checkout hdl_2019_r2; // or latest release cd hdl/projects/ad9081_fmca_ebz/vcu118 make
2. Build the Linux files
Instructions on how to build the MicroBlaze Linux kernel and devicetrees from source can be found here:
make simpleImage.vcu118_ad9081_m8_l4
Latest released files can be downloaded from here
3. Program the board
First we need to prepare a working directory where we will gather all the required binary files.
From the HDL build directory locate the system_top.bit and copy it to the working directory.
From the Linux build directory locate the simpleImage and copy it to the working directory.
mkdir <working_dir> cp <hdl_repo_dir>/projects/ad9081_fmca_ebz_vcu118.runs/impl_1/system_top.bit <working_dir> cp <linux_repo_dir>/arch/microblaze/boot/simpleImage.vcu118_ad9081_m8_l4.strip <working_dir>
Next step is to program the board with xsct or similar tool. See generic instructions for programming the MicroBlaze bases systems here Boot Kernel on FPGA Microblaze
xsct% connect xsct% fpga -f system_top.bit xsct% after 1000 xsct% target 3 xsct% dow simpleImage.vcu118_ad9081_m8_l4.strip xsct% after 1000 xsct% con xsct% disconnect
When using the downloaded archives, simply open xsdb and source
run.tcl
Linux BOOT messages
Login Information
- user: root
- password: analog
The following devices should be present:
This specifies any shell prompt running on the target
# iio_info | grep iio:device
iio:device0: hmc7044
iio:device1: axi-ad9081-tx-hpc (buffer capable)
iio:device2: axi-ad9081-rx-hpc (buffer capable)
All links should be in DATA without errors:
This specifies any shell prompt running on the target
# jesd_status -s (DEVICES) Found 2 JESD204 Link Layer peripherals (0): axi-jesd204-rx/44a90000.axi-jesd204-rx [*] (1): axi-jesd204-tx/44b90000.axi-jesd204-tx (STATUS) Link is enabled Link Status DATA Measured Link Clock (MHz) 249.998 Reported Link Clock (MHz) 250.000 Measured Device Clock (MHz) 250.000 Reported Device Clock (MHz) 250.000 Desired Device Clock (MHz) 250.000 Lane rate (MHz) 10000.000 Lane rate / 40 (MHz) 250.000 LMFC rate (MHz) 7.812 SYSREF captured Yes SYSREF alignment error No SYNC~ (LANE STATUS) Lane# 0 1 2 3 Errors 0 0 0 0 Latency (Multiframes/Octets) 1/22 1/20 1/25 1/21 CGS State DATA DATA DATA DATA Initial Frame Sync Yes Yes Yes Yes Initial Lane Alignment Sequence Yes Yes Yes Yes
4. Connect to board with IIO Scope
From the UART console find out the board IP address that was allocated by the DHCP server. If you do not use a DHCP server manually assign an IP to the board Ethernet port.
5. Capture data with IIO Scope
IIO Oscilloscope Remote
Please see also here:Oscilloscope
The IIO Oscilloscope application can be used locally on FPGA platforms featuring a graphical desktop environment such as ZCU102 or ZC706, however for VCU118 we must use the remote network connection.
When using the remote option, once you logged in to the Linux terminal you need to check the IP address of the using the ifconfig command to see if there was any address assigned by a DHCP server. If not, you need to manually set an address with ifconfig in the same address space your PC is using.
Once the IIO Osc application is launched goto Settings → Connect and enter the IP address of the target in the popup window.
IIO OSC AD9081 Capture Window
Introduction
Main receivers are handled by the axi-ad9081-rx-hpc IIO device, The number of channels depend on the JESD mode (M) parameter and can vary from case to case. When using complex IQ, two channels index by _i and _q from a receiver.
Screenshots
Time Domain View
Frequency Domain View
AD9081 Plugin Description
The AD9081 plugin works with the IIO Oscilloscope. You always use the latest version if possible. Changing any field will immediately write changes which have been made to the AD9081 settings to the hardware, and then read it back to make sure the setting is valid. If you want to set something that the GUI changes to a different number, that either means that GUI is rounding (sorry), or the hardware (either the AD9081 or the FPGA fabric) does not support that mode/precision.
If you want to go play with /sys/bus/iio/devices/…. and manipulate the devices behind the back of the GUI, it's still possible to see the settings by clicking the Reload Settings button at the bottom of the GUI.
The AD9081 view is divided in three sections:
- Receive Chain
- Transmit Chain
- FPGA Settings
Receive Chain
- ADC Rate(MHz): Displays the ADC Sample Rate. Read More
- ADC Nyquist Zone Control: Selects the Nyquist Zone. Read More
- RX Main NCO Frequency Control: Controls the Main NCO. Frequency Read More
- RX Main NCO Phase Control: Controls the Main NCO Phase. Read More
- RX Channel NCO Frequency Control: Controls the Channel NCO Frequency. Read More
- RX Channel NCO Phase Control: Controls the Channel NCO Phase. Read More
Transmit Chain
- DAC Rate(MHz): Displays the DAC Sample Rate. Read More
- TX Main NCO Frequency Control: Controls the Main NCO Frequency. Read More
- TX Main NCO Phase Control: Controls the Main NCO Phase. Read More
- TX Channel NCO Frequency Control: Controls the Channel. NCO Frequency Read More
- TX Channel NCO Phase Control: Controls the Channel NCO Phase. Read More
- TX NCO Channel Digital Gain: Controls the Channel NCO digital gain. Read More
- TX NCO Test Tone Modes: Controls the Test Tone generation. Read More
FPGA Settings
Transmit/DDS
The plugin provides several options on how the transmitted data is generated.
It is possible to either use the built-in two tone Direct Digital Synthesizer (DDS) to transmit a bi-tonal signal on channels I and Q of the DAC. Or it is possible to use the Direct Memory Access (DMA) facility to transmit custom data that you have stored in a file.
This can be achieved by selecting one of the following options listed by the DDS Mode:
One CW Tone
In One CW Tone mode one continuous wave (CW) tone will be outputted. The plugin displays the controls to set the Frequency, Amplitude and Phase for just one tone and makes sure that the amplitude of the other tone is set to 0. The resulting signal will be outputted on the Channel I of the DAC and the exact same signal but with a difference in phase of 90 degrees will be outputted on the Channel Q of the DAC.
Two CW Tone
In Two CW Tone mode two continuous wave (CW) tones will be outputted. The plugin displays the controls to set the frequencies F1 and F2, amplitudes A1 and A2, phases P1 and P2 for the two tones. The resulting signal will be outputted on the Channel I of the DAC and the exact same signal but with a difference in phase of 90 degrees will be outputted on the Channel Q of the DAC.
Independent I/Q Control
In Independent I/Q Control the plugin displays the controls to set the frequencies, amplitudes and phases for the two tones that will be outputted on channel I and additionally it allows for the two tones that will be outputted on channel Q of the DAC to be configured independently.
Note: The bi-tonal signal (T) is defined as the sum of two tones:
T(t) = A1 * sin(2 * p * F1 * t + P1) + A2 * sin(2 * p * F2 * t + P2),
where A-amplitude, F-frequency, P-phase of a tone.
DAC Buffer Output
The file selector under the File Selection section is used to locate and choose the desired data file. Under the DAC Channels section the enabled channels will be used to transmit the data stored in the file. To finalize the process, a click on the Load button is required.
Restrictions:
- There are two types of files than can be loaded: .txt or .mat. The IIO-Oscilloscope comes with several data files that can be used. If you want to create your own data files please take a look at the Basic IQ Data Files documentation first.
- Due to hardware limitation only specific combinations of enabled channels are possible. You can enable a total of 1, 2, 4, etc. channels. If 1 channel is enabled then it can be any of them. If two channels are enabled then channels 0, 1 or channels 2, 3 can be enabled and so on.
Disable
In this mode both DDS and DMA are disabled causing the DAC channels to stop transmitting any data.
Upon pressing Reload Settings button the values will be reloaded with the corresponding driver values. Useful in scenarios where the diver values get changed outside this plugin and a refresh on plugin's values is needed.
Some plugin values will be rounded to the nearest value supported by the hardware.
Useful links
-
-
-
-
- MATLAB support is provided through the High Speed Converter Toolbox
-
- PYTHON support is provided through the Device Specific Python Interfaces For IIO Drivers
- Product Datasheet
Support
Analog Devices will provide limited online support for anyone using the reference design with Analog Devices components via the EngineerZone.
resources/eval/user-guides/ad9081_fmca_ebz/quickstart/microblaze.txt · Last modified: 24 Apr 2023 09:37 by Michael Hennerich