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13 Jun 2023 10:55 UTIL_ADXCVR core for Xilinx devices – Fix spelling mistakes Iulia Moldovan +14 B (current)
29 Nov 2022 17:29 UTIL_ADXCVR core for Xilinx devices – Note in [Design Guidelines] Andrei Dragomir +81 B
08 Dec 2021 11:03 UTIL_ADXCVR core for Xilinx devices – [Design Guidelines] Laszlo Nagy +1.3 KB
13 Oct 2021 08:56 UTIL_ADXCVR core for Xilinx devices – Edit footer Iulia Moldovan +27 B
11 Oct 2021 14:42 UTIL_ADXCVR core for Xilinx devices – Edit next page to be Using and modifying the HDL design Iulia Moldovan +18 B
14 Jan 2021 05:38 UTIL_ADXCVR core for Xilinx devices – use xilinx> interwiki links Robin Getz -144 B
28 Jan 2020 22:34 UTIL_ADXCVR core for Xilinx devices – Fix broken link Adrian Costina +3 B
23 Oct 2019 15:03 UTIL_ADXCVR core for Xilinx devices – [UTIL_ADXCVR core for Xilinx devices] Add mention of GTY support Adrian Costina +137 B
16 Oct 2019 12:58 UTIL_ADXCVR core for Xilinx devices – Add link to the guide for porting to other Xilinx transceivers Adrian Costina +95 B
15 Nov 2018 10:45 UTIL_ADXCVR core for Xilinx devices – [Configuration Parameters] Delete deprecated paramter. Istvan Csomortani -159 B
04 May 2018 11:32 UTIL_ADXCVR core for Xilinx devices – [Configuration Parameters] Add {RX,TX}_LANE_INVERT Lars-Peter Clausen +248 B
05 Dec 2017 23:53 UTIL_ADXCVR core for Xilinx devices – Kin Chan ±0 B
22 Feb 2017 19:33 UTIL_ADXCVR core for Xilinx devices – [References] Lars-Peter Clausen ±0 B
22 Feb 2017 14:45 UTIL_ADXCVR core for Xilinx devices – Section header level. H1 for first level, H2 for second level Lars-Peter Clausen ±0 B
22 Feb 2017 14:24 UTIL_ADXCVR core for Xilinx devices – [Software Guidelines] Use internal instead of external link to AXI_ADXCR Lars-Peter Clausen ±0 B
25 Nov 2016 11:29 UTIL_ADXCVR core for Xilinx devices – Add references Istvan Csomortani ±0 B
17 Nov 2016 17:38 UTIL_ADXCVR core for Xilinx devices – created Istvan Csomortani ±0 B

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