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This version is outdated by a newer approved version.DiffThis version (22 Feb 2017 15:19) was approved by Lars-Peter Clausen.The Previously approved version (22 Feb 2017 14:24) is available.Diff

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Table of Contents

UTIL_ADXCVR core for Xilinx devices

The util_adxcvr IP core instantiate a Gigabit Transceiver (GT) and set's up the required configuration. Basically is a simple wrapper file for a GT* Column, exposing just the necessary ports and attributes.

To understand the below wiki page is important to have a basic understanding about High Speed Serial I/O interfaces and Gigabit Serial Transceivers. To find more information about these technologies please visit the Xilinx's solution center.

Currently this IP supports three different GT type:

Features

  • Supports GTX2, GTH3 and GTH4
  • Exposes all the necessary attribute for QPLL/CPLL configuration
  • Supports shared transceiver mode
  • Support dynamic reconfiguration
  • RX Eye Scan

Block Diagram

The following diagram shows a GTXE2 Column, which contains four GT Quad. Each quad contains a GTEX2_COMMON and four GTXE2_CHANNEL primitive.

GTXE2 Column

Configuration Parameters

Name Description Default Value
XCVR_TYPE Define the current GT type, GTXE2(0), GTHE3(1), GTHE4(3) 0
QPLL_REFCLK_DIV QPLL reference clock divider M, see User Guide for more info 1
QPLL_FBDIV_RATIO QPLL reference clock divider N ratio, see User Guide for more info 1
QPLL_CFG Configuration settings for QPLL, see User Guide for more info 27'h0680181
QPLL_FBDIV QPLL reference clock divider N, see User Guide for more info 10'b0000110000
CPLL_FBDIV CPLL feedback divider N2 settings, see User Guide for more info 2
CPLL_FBDIV_45 CPLL reference clock divider N1 settings, see User Guide for more info 5
CPLL_TX_OR_RX_N Set the control AXI core for the PLL's, if is set CPLL is controlled by TX and QPLL is controlled by RX, if is reset vice versa. 0
TX_NUM_OF_LANES Number of transmit lanes. 8
TX_OUT_DIV CPLL/QPLL output clock divider D for the TX datapath, see User Guide for more info 1
TX_CLK25_DIV Divider for internal 25 MHz clock for the TX datapath, see User Guide for more info 20
RX_NUM_OF_LANES Number of transmit lanes 8
RX_OUT_DIV CPLL/QPLL output clock divider D for the RX datapath, see User Guide for more info 1
RX_CLK25_DIV Divider for internal 25 MHz clock for the RX datapath, see User Guide for more info 20
RX_DFE_LPM_CFG Configure the GT use modes, LPM or DFE, see User Guide for more info 16'h0104
RX_PMA_CFG Search for PMA_RSV in User Guide for more info 32'h001e7080
RX_CDR_CFG Configure the RX clock data recovery circuit for GTXE2, see User Guide for more info 72'h0b000023ff10400020

Interface

Interface Pin Type Description
Microprocessor clock and reset
up_clk input System clock, running on 100 MHz
up_rstn input System reset, the same as AXI memory map slave interface reset
PLL reference clock
qpll_ref_clk_0 input Reference clock for the QPLL
cpll_ref_clk_0 input Reference clock for the CPLL
RX interface
rx_*_p input Positive differential serial data input
rx_*_n input Negative differential serial data input
rx_out_clk_* output Core logic clock output. Frequency = serial line rate/40
rx_clk_* input Core logic clock loop-back input
rx_charisk_* output[ 3:0] RX Char is K to the JESD204B IP
rx_disperr_* output[ 3:0] RX disparity error to the JESD204B IP
rx_notintable_* output[ 3:0] RX Not In Table to the JESD204B IP
rx_data_* output[31:0] RX data to the JESD204B IP
rx_calign_* input RX enable comma alignment from the JESD204B IP
TX interface
tx_*_p output Positive differential serial output
tx_*_n output Negative differential serial output
tx_out_clk_* output Core logic clock output. Frequency = lane rate/40
tx_clk_* input Core logic clock loop-back input
tx_charisk_* input[ 3:0] TX Char is K from the JESD204B IP
tx_data_* input[31:0] TX data from the JESD204B IP
Common DRP interface
up_cm_* IO The common DRP interface, must be connected to the equivalent DRP ports of AXI_ADXCVR. This is a QUAD interface, shared by four transceiver lanes. This interface is available only if parameter QPLL_ENABLE is set to 0x1.
Channel DRP interface
up_ch_* IO The channel DRP interface, must be connected to the equivalent DRP ports of AXI_ADXCVR. This is a channel interface, one per each transceiver lane.
Eye Scan DRP interface
up_es_* IO The Eye-Scan DRP interface, must be connected to the equivalent DRP ports of UTIL_ADXCVR. This is a channel interface, one per each transceiver lane. This interface is available only if parameter TX_OR_RX_N is set to 0x0.

Design Guidelines

TBD

Software Guidelines

The software can configure this core through the AXI_ADXCVR IP core.

References

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resources/fpga/docs/util_xcvr.1487771149.txt.gz · Last modified: 22 Feb 2017 14:45 by Lars-Peter Clausen

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