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| resources:fpga:docs:util_xcvr [11 Oct 2021 14:42] – Edit next page to be Using and modifying the HDL design Iulia Moldovan | resources:fpga:docs:util_xcvr [13 Jun 2023 10:55] (current) – Fix spelling mistakes Iulia Moldovan |
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| ====== UTIL_ADXCVR core for Xilinx devices ====== | ====== UTIL_ADXCVR core for Xilinx devices ====== |
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| The [[https://github.com/analogdevicesinc/hdl/tree/master/library/xilinx/util_adxcvr|util_adxcvr]] IP core instantiate a Gigabit Transceiver (GT) and set's up the required configuration. Basically is a simple wrapper file for a GT* Column, exposing just the necessary ports and attributes. | The [[https://github.com/analogdevicesinc/hdl/tree/master/library/xilinx/util_adxcvr|util_adxcvr]] IP core instantiates a Gigabit Transceiver (GT) and sets up the required configuration. Basically, it is a simple wrapper file for a GT* Column, exposing just the necessary ports and attributes. |
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| <note important>To understand the below wiki page is important to have a basic understanding about [[http://lmgtfy.com/?q=High+Speed+Serial+IO|High Speed Serial I/O]] interfaces and Gigabit Serial Transceivers. To find more information about these technologies please visit the [[xilinx>support/answers/37181.html|Xilinx's solution center]]. | <note important>To understand the below wiki page is important to have a basic understanding about [[http://lmgtfy.com/?q=High+Speed+Serial+IO|High Speed Serial I/O]] interfaces and Gigabit Serial Transceivers. To find more information about these technologies, please visit the [[xilinx>support/answers/37181.html|Xilinx's solution center]]. |
| </note> | </note> |
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| Currently this IP supports three different GT type: | Currently this IP supports three different GT types: |
| * GTXE2 ([[xilinx>support/documentation/user_guides/ug476_7Series_Transceivers.pdf|7 Series devices]]) | * GTXE2 ([[xilinx>support/documentation/user_guides/ug476_7Series_Transceivers.pdf|7 Series devices]]) |
| * GTHE3 ([[xilinx>support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf|Ultrascale and Ultrascale+]]) | * GTHE3 ([[xilinx>support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf|Ultrascale and Ultrascale+]]) |
| * GTHE4 ([[xilinx>support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf|Ultrascale and Ultrascale+]]) | * GTHE4 ([[xilinx>support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf|Ultrascale and Ultrascale+]]) |
| * GTYE4 ([[xilinx>support/documentation/user_guides/ug578-ultrascale-gty-transceivers.pdf|Ultrascale and Ultrascale+]]) | * GTYE4 ([[xilinx>support/documentation/user_guides/ug578-ultrascale-gty-transceivers.pdf|Ultrascale and Ultrascale+]]) |
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| ===== Features ===== | ===== Features ===== |
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| * Supports GTX2, GTH3 and GTH4 \\ | * Supports GTX2, GTH3 and GTH4 \\ |
| * Exposes all the necessary attribute for QPLL/CPLL configuration \\ | * Exposes all the necessary attributes for QPLL/CPLL configuration \\ |
| * Supports shared transceiver mode \\ | * Supports shared transceiver mode \\ |
| * Support dynamic reconfiguration \\ | * Supports dynamic reconfiguration \\ |
| * RX Eye Scan | * RX Eye Scan |
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| ===== Block Diagram ===== | ===== Block Diagram ===== |
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| The following diagram shows a GTXE2 Column, which contains four GT Quad. Each quad contains a GTEX2_COMMON and four GTXE2_CHANNEL primitive. | The following diagram shows a GTXE2 Column, which contains four GT Quads. Each quad contains a GTEX2_COMMON and four GTXE2_CHANNEL primitives. |
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| {{ :resources:fpga:docs:hdl:gtx_column.png | GTXE2 Column }} | {{ :resources:fpga:docs:hdl:gtx_column.png | GTXE2 Column }} |
| | ''RX_CDR_CFG'' | Configure the RX clock data recovery circuit for GTXE2, see User Guide for more info | 72'h0b000023ff10400020 | | | ''RX_CDR_CFG'' | Configure the RX clock data recovery circuit for GTXE2, see User Guide for more info | 72'h0b000023ff10400020 | |
| | ''RX_LANE_INVERT'' | Per lane polarity inversion. Set the n-th bit to invert the polarity of the n-th receive lane. | 0 | | | ''RX_LANE_INVERT'' | Per lane polarity inversion. Set the n-th bit to invert the polarity of the n-th receive lane. | 0 | |
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| ===== Interface ===== | ===== Interface ===== |
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| | **Eye Scan DRP interface** |||| | | **Eye Scan DRP interface** |||| |
| | | ''up_es_*'' | ''IO'' | The Eye-Scan DRP interface, must be connected to the equivalent DRP ports of UTIL_ADXCVR. This is a channel interface, one per each transceiver lane. This interface is available only if parameter TX_OR_RX_N is set to 0x0. | | | | ''up_es_*'' | ''IO'' | The Eye-Scan DRP interface, must be connected to the equivalent DRP ports of UTIL_ADXCVR. This is a channel interface, one per each transceiver lane. This interface is available only if parameter TX_OR_RX_N is set to 0x0. | |
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| ===== Design Guidelines ===== | ===== Design Guidelines ===== |
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| For porting on different Xilinx transceiver types, there is the following [[.:xgt_wizard|guide]]. | <note> |
| | Please refer to [[.:xgt_wizard|Xilinx FPGAs Transceivers Wizard]] to generate the optimal parameters needed to configure the transceivers for your project. |
| | </note> |
| | ==== Physical constraints considerations ==== |
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| | The util_adxcvr allocates resources/quads (channels and common) sequentially. Meaning, if you have 8 lanes it will insert two quads, 4 channels and a common block for each quad. |
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| | Channels within a quad are tightly coupled to the common block, the placement of the channel resources can be permuted within a quad and is affected by the constraint file with the restriction that rx_<N>_p/n connect to tx_<N>_p/n must connect to the same channel. |
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| | Supposing we have the following pin constraints and connections to the util_adxcvr: |
| | {{ :resources:fpga:docs:xcvr_mapping_example.jpg?nolink |}} |
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| | So in this case we end up with a conflict during implementation: |
| | {{ :resources:fpga:docs:xcvr_conflict.jpg?nolink |}} |
| | We have to ensure that in implementation the mapping is correct either by rearranging the Rx connections |
| | {{ :resources:fpga:docs:xcvr_rx_rearrangement.jpg?nolink |}} |
| | or by rearranging the Tx connections of the util_adxcvr: |
| | {{ :resources:fpga:docs:xcvr_tx_rearrangement.jpg?nolink |}} |
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| | In such cases, when rearrangement is required due placement constraints, complementary reordering is required either in the converter device (lane crossbars) or inside the FPGA between the physical and link layer, to connect the logical lanes with the same index on both end of the link. |
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| ===== Software Guidelines ===== | ===== Software Guidelines ===== |
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| The software can configure this core through the [[.:axi_adxcvr|AXI_ADXCVR]] IP core. | The software can configure this core through the [[.:axi_adxcvr|AXI_ADXCVR]] IP core. |
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| ===== References ===== | ===== References ===== |
| * [[xilinx>support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf|UltraScale Architecture GTH Transceivers]] | * [[xilinx>support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf|UltraScale Architecture GTH Transceivers]] |
| * [[xilinx>support/documentation/user_guides/ug578-ultrascale-gty-transceivers.pdf|UltraScale Architecture GTY Transceivers]] | * [[xilinx>support/documentation/user_guides/ug578-ultrascale-gty-transceivers.pdf|UltraScale Architecture GTY Transceivers]] |
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| ===== More Information ===== | ===== More Information ===== |
| * [[resources:fpga:peripherals:jesd204|JESD204B High-Speed Serial Interface Support]] | * [[resources:fpga:peripherals:jesd204|JESD204B High-Speed Serial Interface Support]] |
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