| Both sides previous revisionPrevious revisionNext revision | Previous revision |
| resources:fpga:docs:util_xcvr [22 Feb 2017 14:24] – [Software Guidelines] Use internal instead of external link to AXI_ADXCR Lars-Peter Clausen | resources:fpga:docs:util_xcvr [13 Jun 2023 10:55] (current) – Fix spelling mistakes Iulia Moldovan |
|---|
| ===== UTIL_ADXCVR core for Xilinx devices ===== | ====== UTIL_ADXCVR core for Xilinx devices ====== |
| |
| The [[https://github.com/analogdevicesinc/hdl/tree/dev/library/xilinx/util_adxcvr|util_adxcvr]] IP core instantiate a Gigabit Transceiver (GT) and set's up the required configuration. Basically is a simple wrapper file for a GT* Column, exposing just the necessary ports and attributes. | The [[https://github.com/analogdevicesinc/hdl/tree/master/library/xilinx/util_adxcvr|util_adxcvr]] IP core instantiates a Gigabit Transceiver (GT) and sets up the required configuration. Basically, it is a simple wrapper file for a GT* Column, exposing just the necessary ports and attributes. |
| |
| <note important>To understand the below wiki page is important to have a basic understanding about [[http://lmgtfy.com/?q=High+Speed+Serial+IO|High Speed Serial I/O]] interfaces and Gigabit Serial Transceivers. To find more information about these technologies please visit the [[https://www.xilinx.com/support/answers/37181.html|Xilinx's solution center]]. | <note important>To understand the below wiki page is important to have a basic understanding about [[http://lmgtfy.com/?q=High+Speed+Serial+IO|High Speed Serial I/O]] interfaces and Gigabit Serial Transceivers. To find more information about these technologies, please visit the [[xilinx>support/answers/37181.html|Xilinx's solution center]]. |
| </note> | </note> |
| |
| Currently this IP supports three different GT type: | Currently this IP supports three different GT types: |
| * GTXE2 ([[https://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf|7 Series devices]]) | * GTXE2 ([[xilinx>support/documentation/user_guides/ug476_7Series_Transceivers.pdf|7 Series devices]]) |
| * GTHE3 ([[https://www.xilinx.com/support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf|Ultrascale and Ultrascale+]]) | * GTHE3 ([[xilinx>support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf|Ultrascale and Ultrascale+]]) |
| * GTHE4 ([[https://www.xilinx.com/support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf|Ultrascale and Ultrascale+]]) | * GTHE4 ([[xilinx>support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf|Ultrascale and Ultrascale+]]) |
| | * GTYE4 ([[xilinx>support/documentation/user_guides/ug578-ultrascale-gty-transceivers.pdf|Ultrascale and Ultrascale+]]) |
| |
| ==== Features ==== | |
| | ===== Features ===== |
| |
| * Supports GTX2, GTH3 and GTH4 \\ | * Supports GTX2, GTH3 and GTH4 \\ |
| * Exposes all the necessary attribute for QPLL/CPLL configuration \\ | * Exposes all the necessary attributes for QPLL/CPLL configuration \\ |
| * Supports shared transceiver mode \\ | * Supports shared transceiver mode \\ |
| * Support dynamic reconfiguration \\ | * Supports dynamic reconfiguration \\ |
| * RX Eye Scan | * RX Eye Scan |
| |
| ==== Block Diagram ==== | |
| |
| The following diagram shows a GTXE2 Column, which contains four GT Quad. Each quad contains a GTEX2_COMMON and four GTXE2_CHANNEL primitive. | ===== Block Diagram ===== |
| | |
| | The following diagram shows a GTXE2 Column, which contains four GT Quads. Each quad contains a GTEX2_COMMON and four GTXE2_CHANNEL primitives. |
| |
| {{ :resources:fpga:docs:hdl:gtx_column.png | GTXE2 Column }} | {{ :resources:fpga:docs:hdl:gtx_column.png | GTXE2 Column }} |
| |
| ==== Configuration Parameters ==== | ===== Configuration Parameters ===== |
| |
| ^ Name ^ Description ^ Default Value^ | ^ Name ^ Description ^ Default Value^ |
| | ''XCVR_TYPE'' | Define the current GT type, GTXE2(0), GTHE3(1), GTHE4(3) | 0 | | | ''XCVR_TYPE'' | Define the current GT type, GTXE2(0), GTHE3(1), GTHE4(2) | 0 | |
| | ''QPLL_REFCLK_DIV'' | QPLL reference clock divider M, see User Guide for more info | 1 | | | ''QPLL_REFCLK_DIV'' | QPLL reference clock divider M, see User Guide for more info | 1 | |
| | ''QPLL_FBDIV_RATIO'' | QPLL reference clock divider N ratio, see User Guide for more info | 1 | | | ''QPLL_FBDIV_RATIO'' | QPLL reference clock divider N ratio, see User Guide for more info | 1 | |
| | ''CPLL_FBDIV'' | CPLL feedback divider N2 settings, see User Guide for more info | 2 | | | ''CPLL_FBDIV'' | CPLL feedback divider N2 settings, see User Guide for more info | 2 | |
| | ''CPLL_FBDIV_45'' | CPLL reference clock divider N1 settings, see User Guide for more info | 5 | | | ''CPLL_FBDIV_45'' | CPLL reference clock divider N1 settings, see User Guide for more info | 5 | |
| | ''CPLL_TX_OR_RX_N'' | Set the control AXI core for the PLL's, if is set CPLL is controlled by TX and QPLL is controlled by RX, if is reset vice versa. | 0 | | |
| | ''TX_NUM_OF_LANES'' | Number of transmit lanes. | 8 | | | ''TX_NUM_OF_LANES'' | Number of transmit lanes. | 8 | |
| | ''TX_OUT_DIV'' | CPLL/QPLL output clock divider D for the TX datapath, see User Guide for more info | 1 | | | ''TX_OUT_DIV'' | CPLL/QPLL output clock divider D for the TX datapath, see User Guide for more info | 1 | |
| | ''TX_CLK25_DIV'' | Divider for internal 25 MHz clock for the TX datapath, see User Guide for more info | 20 | | | ''TX_CLK25_DIV'' | Divider for internal 25 MHz clock for the TX datapath, see User Guide for more info | 20 | |
| | | ''TX_LANE_INVERT'' | Per lane polarity inversion. Set the n-th bit to invert the polarity of the n-th transmit lane. | 0 | |
| | ''RX_NUM_OF_LANES'' | Number of transmit lanes | 8 | | | ''RX_NUM_OF_LANES'' | Number of transmit lanes | 8 | |
| | ''RX_OUT_DIV'' | CPLL/QPLL output clock divider D for the RX datapath, see User Guide for more info | 1 | | | ''RX_OUT_DIV'' | CPLL/QPLL output clock divider D for the RX datapath, see User Guide for more info | 1 | |
| | ''RX_PMA_CFG'' | Search for PMA_RSV in User Guide for more info | 32'h001e7080 | | | ''RX_PMA_CFG'' | Search for PMA_RSV in User Guide for more info | 32'h001e7080 | |
| | ''RX_CDR_CFG'' | Configure the RX clock data recovery circuit for GTXE2, see User Guide for more info | 72'h0b000023ff10400020 | | | ''RX_CDR_CFG'' | Configure the RX clock data recovery circuit for GTXE2, see User Guide for more info | 72'h0b000023ff10400020 | |
| | | ''RX_LANE_INVERT'' | Per lane polarity inversion. Set the n-th bit to invert the polarity of the n-th receive lane. | 0 | |
| |
| ==== Interface ==== | |
| | ===== Interface ===== |
| |
| ^ Interface ^ Pin ^ Type ^ Description ^ | ^ Interface ^ Pin ^ Type ^ Description ^ |
| | | ''up_es_*'' | ''IO'' | The Eye-Scan DRP interface, must be connected to the equivalent DRP ports of UTIL_ADXCVR. This is a channel interface, one per each transceiver lane. This interface is available only if parameter TX_OR_RX_N is set to 0x0. | | | | ''up_es_*'' | ''IO'' | The Eye-Scan DRP interface, must be connected to the equivalent DRP ports of UTIL_ADXCVR. This is a channel interface, one per each transceiver lane. This interface is available only if parameter TX_OR_RX_N is set to 0x0. | |
| |
| ==== Design Guidelines ==== | |
| |
| TBD | ===== Design Guidelines ===== |
| |
| ==== Software Guidelines ==== | <note> |
| | Please refer to [[.:xgt_wizard|Xilinx FPGAs Transceivers Wizard]] to generate the optimal parameters needed to configure the transceivers for your project. |
| | </note> |
| | ==== Physical constraints considerations ==== |
| | |
| | The util_adxcvr allocates resources/quads (channels and common) sequentially. Meaning, if you have 8 lanes it will insert two quads, 4 channels and a common block for each quad. |
| | |
| | Channels within a quad are tightly coupled to the common block, the placement of the channel resources can be permuted within a quad and is affected by the constraint file with the restriction that rx_<N>_p/n connect to tx_<N>_p/n must connect to the same channel. |
| | |
| | Supposing we have the following pin constraints and connections to the util_adxcvr: |
| | {{ :resources:fpga:docs:xcvr_mapping_example.jpg?nolink |}} |
| | |
| | So in this case we end up with a conflict during implementation: |
| | {{ :resources:fpga:docs:xcvr_conflict.jpg?nolink |}} |
| | We have to ensure that in implementation the mapping is correct either by rearranging the Rx connections |
| | {{ :resources:fpga:docs:xcvr_rx_rearrangement.jpg?nolink |}} |
| | or by rearranging the Tx connections of the util_adxcvr: |
| | {{ :resources:fpga:docs:xcvr_tx_rearrangement.jpg?nolink |}} |
| | |
| | In such cases, when rearrangement is required due placement constraints, complementary reordering is required either in the converter device (lane crossbars) or inside the FPGA between the physical and link layer, to connect the logical lanes with the same index on both end of the link. |
| | |
| | |
| | ===== Software Guidelines ===== |
| |
| The software can configure this core through the [[.:axi_adxcvr|AXI_ADXCVR]] IP core. | The software can configure this core through the [[.:axi_adxcvr|AXI_ADXCVR]] IP core. |
| |
| ==== References ==== | |
| * [[https://www.xilinx.com/products/technology/high-speed-serial.html|High Speed Serial]] | ===== References ===== |
| * [[https://www.xilinx.com/support/documentation/user_guides/ug476_7Series_Transceivers.pdf|7 Series FPGAs GTX/GTH Transceivers]] | |
| * [[https://www.xilinx.com/support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf|UltraScale Architecture GTH Transceivers]] | * [[xilinx>products/technology/high-speed-serial.html|High Speed Serial]] |
| * [[https://www.xilinx.com/support/documentation/user_guides/ug578-ultrascale-gty-transceivers.pdf|UltraScale Architecture GTY Transceivers]] | * [[xilinx>support/documentation/user_guides/ug476_7Series_Transceivers.pdf|7 Series FPGAs GTX/GTH Transceivers]] |
| {{navigation #axi_ip|AXI IP#hdl|Main page#util_ip|UTIL IP Cores}} | * [[xilinx>support/documentation/user_guides/ug576-ultrascale-gth-transceivers.pdf|UltraScale Architecture GTH Transceivers]] |
| | * [[xilinx>support/documentation/user_guides/ug578-ultrascale-gty-transceivers.pdf|UltraScale Architecture GTY Transceivers]] |
| | |
| | |
| | ===== More Information ===== |
| | |
| | * [[resources:fpga:peripherals:jesd204|JESD204B High-Speed Serial Interface Support]] |
| | |
| | {{navigation HDL User Guide#ip_cores|IP cores#hdl|Main page#tips|Using and modifying the HDL design}} |
