This version is outdated by a newer approved version.
This version (12 Jul 2023 22:01) is a draft.
Approvals: 0/1The Previously approved version (29 May 2023 10:36) is available.
This version (12 Jul 2023 22:01) is a draft.Approvals: 0/1The Previously approved version (29 May 2023 10:36) is available.
This is an old revision of the document!
Table of Contents
EVAL-CN0585-FMCZ User Guide
The EVAL-CN0585-FMCZ Low Latency Development Kit (LLDK) board is a development platform consisting of 4 x 16-bit ADC channels and 4 x 16-bit DAC channels that are interfaced with an FPGA through the FMC Low Pin Count (LPC) Connector.
The EVAL-CN0585-FMCZ board provides a complete data acquisition and signal generation platform with onboard power rails, voltage monitoring, logic level translation, general purpose I/O, I2C, SPI, and an Analog Front End(AFE) board connector.
The key performance benefit of the EVAL-CN0585-FMCZ is the ability to perform a complete capture and conversion of precision analog input data in <70ns with the ADC module and generate a settled full-scale analog output in <200ns from initial data written to the DAC.
Figure 1. EVAL-CN0585-FMCZ Board Top
Figure 2. EVAL-CN0585-FMCZ Board Bottom
Figure 3. EVAL-CN0585-FMCZ Simplified Block Diagram
Connections and Configurations
Receive Channel
The EVAL-CN0585-FMCZ board has four ADAQ23876 16Bit 15MSPS Data Acquisition µModules to capture analog data from the AFE board connector. The Data Acquisition µModules are configured to simultaneously sample the four input channels. The data acquired by the ADAQ23876 is routed to the FPGA through the FMC LPC connector using a serial low voltage differential signaling (LVDS) digital interface in a two-lane output mode. The ADAQ23876 has pin configurable input voltage span with configurable gain/attenuation options: 0.37, 0.73, 0.87, 1.38, and 2.25, providing input voltage span ranges of ±10 V, ±5 V, ±4.096 V, ±2.5 V, and ±1.5 V. The gain/attenuation functions are accessible through the AFE board connector pins. As an example the EVAL-CN0584-EBZ is available for Hardware In the Loop (HIL) applications.
Transmit Channel
The EVAL-CN0585-FMCZ board has two AD3552R 16-bit 33MUPS DACs that provide four analog output signals to the AFE board connector. Data is transferred to the AD3552R DAC from the FPGA through the FMC LPC connector using a Quad-SPI dual data rate interface.
The AD3552R has a pin-configurable output voltage span that can be configured through the AFE board connector. Multiple output span ranges can be configured, such as 0 V to 2.5 V, 0 V to 5 V, −5 V to +5 V, −10 V to +10 V, and custom intermediate ranges with full 16-bit resolution. (Refer to Table 3)
Voltage Reference
The default ADC reference configuration uses the internal 2.048 V, ±0.1% accurate, 20 ppm/°C max voltage reference. For more stringent use cases where the accuracy and temperature drift is an issue, an external LTC6655 2.048 V, ±0.025% accurate, 2 ppm/°C max voltage reference can be used.
The default DAC reference configuration uses the internal 2.5 V, ±0.3% accurate, 10 ppm/°C max voltage reference. For more stringent use cases where the accuracy and temperature drift is an issue, an external ADR4525 2.5 V, ±0.02% accurate, 2 ppm/°C max voltage reference can be used.
| VREF | Jumper Settings |
|---|---|
| ADC_VREF | Short P5 |
| DAC_VREF | Short P4 |
Table 1. Voltage Reference Settings
Voltage Monitoring
The EVAL-CN0585-FMCZ board provides voltage monitoring capability for the power supply rails. The circuit consists of an AD7291 8-Channel, I2C, 12-Bit SAR ADC, and resistive dividers. Each power rail is connected to AD7291 by resistive dividers as shown in Figure 4.
Figure 4: Power Supply Voltage Monitor Circuit
The negative power supply rails are biased positive with a buffered 2.5V reference supplied by the AD7291.
Calculating the supply voltage from the positive voltage rails can be accomplished using the following equation:
V_(RAIL_POS)=Scale Factor*ADC_Code*2.5V/4095
Calculating the supply voltage from the negative voltage rails can be accomplished using the following equation:
V_(RAIL_NEG)=Scale Factor*(4095-ADC_Code )*2.5V/4095+2.5V
| RF Device | CN0585 Power Rail | Measured Voltage | Actual Voltage |
|---|---|---|---|
| voltage0 | +12 V (AD8065 DAC amp) | 2.26 V | 12 V |
| voltage1 | -12 V (AD8065 DAC amp) | 0.65 V | -12 V |
| voltage2 | +5 V (ADAQ23876 internal amp) | 2.06 V | 5 V |
| voltage3 | -5 V (ADAQ23876 internal amp) | 0.76 V | -5 V |
| voltage4 | +5 V (DAC) | 2.06 V | 5 V |
| voltage5 | +5 V (DAC) | 2.06 V | 5 V |
| voltage6 | +2.5 V (digital) | 2.25 V | 2.5 V |
| voltage7 | +1.8 V (digital) | 1.80 V | 1.8 V |
Table 2. Voltage Scaling
The default I2C address of the AD7291 is 0x20. Resistors R13, R14, R17, and R18 can be used to select alternate addressing.
Logic Level Translators
Several logic-level translators are used on the board to interface with the FMC connector signals and the various logic levels used on the board. The FMC connector signal levels are driven by the VIO voltage supplied from the FPGA board.
GPIO
A GPIO interface is provided by a MAX7301ATL+ I/O Expander connected to the SPI interface on the SPIO_CSB0 chip select interface. The GPIO outputs are controlled by writing to the MAX7301ATL+ via the SPI interface provided on the FMC connector. Four GPIO signals are utilized on the EVAL-CN0585-FMCZ board to control the power-down interface of the ADAQ23875 Data Acquisition µModules. Eight GPIO signals are level-shifted and provided to the AFE board connector for control signals on the AFE board.
I2C
The I2C interface is provided from the FPGA FMC connector and is made available to the EVAL-CN0585-FMCZ board and the user via the AFE board connector. On the EVAL-CN0585-FMCZ board the I2C interface is used to communicate with an EEPROM that is required by the Vita 57.1 Standard for board identification and IO characteristics, and the AD7291 voltage monitoring ADC.
SPI
The EVAL-CN0585-FMCZ board provides an SPI interface for the user on SPI0 from the FMC connector. Communication with the MAX7301ATL+ GPIO expander is enabled by chip select SPIO_CSB0. A second chip select, SPI_CSB1 originates from the FMC interface and connects to the AFE board connector so that the user can attach a custom secondary SPI device to the AFE board. This second SPI0_CSB1 is not initialized in the Linux device tree, as the initialization requires additional information such as SPI transmission mode, phase, and polarity. Two Quad-SPI interfaces (DAC0/1 and DAC2/3) are provided by the FMC interface to handle communications and data transfer to the four AD3552R DAC channels.
Application-specific Analog Front-End Connector
The AFE connector interface provides six signal connections for each of the four ADAQ23876 Data Acquisition µModules. The six signal connections allow the user to set the input voltage range of the differential amplifier input. Configuration resistors, if used, should be placed as close as possible to the AFE board connector. Please refer to the ADAQ23876 Datasheet for more configuration details.
| Input Range | Input Signal on Pins | Feedback Connections |
|---|---|---|
| +/- 10V (Default) | ADCx_IN2P, ADCx_IN2N | ADCx_OUTP and ADCx_IN1N pins Shorted ADCx_OUTN and ADCx_IN1P pins Shorted |
| +/- 5V | ADCx_IN1P, ADCx_IN1N | ADCx_OUTP and ADCx_IN2N pins Shorted ADCx_OUTN and ADCx_IN2P pins Shorted |
| +/- 4.096V | ADCx_IN2P, ADCx_IN2N | No Connect |
| +/- 2.5V | ADCx_IN1P, ADCx_IN1N | No Connect |
| +/- 1.5V | ADCx_IN1P/ADCx_IN2P Shorted ADCx_IN1N/ADCx_IN2N Shorted | No Connect |
Table 3: ADQ23876 Connections for Input Configuration
The AFE connector interface provides three signal connections for each of the four DAC output channels. The three signal connections allow the user to set the output voltage range of the AD3552R DAC. Configuration resistors, if used, should be placed as close as possible to the AFE board connector. The AD3552R uses a current steering DAC architecture with a VREF voltage of 2.5 V. The DAC current is converted to a voltage using an external TIA. The DAC outputs are observed on signals DAC0, DAC1, DAC2, and DAC3. The DACx outputs are fed back into the AD3552R gain configuration pins for each DAC channel. The table below details the configuration connections for each of the output voltage ranges of each of the DAC output channels. Please refer to the AD3552R Datasheet for more configuration details.
| Hardware | AC3552R Settings | |||||||
|---|---|---|---|---|---|---|---|---|
| Channel | Output Span | VZS (V) | VFS (V) | Feedback Connection | CH0_CH1_OUTPUT_range | CHx_GAIN_SCALING_N | CHx_OFFSET | |
| CH0 | +/- 10V (Default) | -10.382 | 10.380 | DAC0 to DAC0_RFB0 | 0x100 | 0 | -245 | |
| +/- 5V | -5.165 | 5.166 | DAC0 to DAC0_RFB0_X2 | 0x011 | 0 | -495 | ||
| 10V | -0.165 | 10.163 | DAC0 to DAC0_RFB0_X2 | 0x010 | 0 | 495 | ||
| 5V | -0.078 | 5.077 | DAC0 to DAC0_RFB0_X1 | 0x001 | 0 | 0 | ||
| 2.5V | -0.198 | 2.701 | DAC0 to DAC0_RFB0_X1 | 0x000 | 3 | -48 | ||
| CH1 | +/- 10V (Default) | -10.382 | 10.380 | DAC1 to DAC1_RFB1 | 0x100 | 0 | -245 | |
| +/- 5V | -5.165 | 5.166 | DAC1 to DAC1_RFB1_X2 | 0x011 | 0 | -495 | ||
| 10V | -0.165 | 10.163 | DAC1 to DAC1_RFB0_X2 | 0x010 | 0 | 495 | ||
| 5V | -0.078 | 5.077 | DAC1 to DAC1_RFB1_X1 | 0x001 | 0 | 0 | ||
| 2.5V | -0.198 | 2.701 | DAC1 to DAC1_RFB1_X1 | 0x000 | 3 | -48 | ||
| CH2 | +/- 10V (Default) | -10.382 | 10.380 | DAC2 to DAC2_RFB0 | 0x100 | 0 | -245 | |
| +/- 5V | -5.165 | 5.166 | DAC2 to DAC2_RFB0_X2 | 0x011 | 0 | -495 | ||
| 10V | -0.165 | 10.163 | DAC2 to DAC2_RFB0_X2 | 0x010 | 0 | 495 | ||
| 5V | -0.078 | 5.077 | DAC2 to DAC2_RFB0_X1 | 0x001 | 0 | 0 | ||
| 2.5V | -0.198 | 2.701 | DAC2 to DAC2_RFB0_X1 | 0x000 | 3 | -48 | ||
| CH3 | +/- 10V (Default) | -10.382 | 10.380 | DAC3 to DAC3_RFB1 | 0x100 | 0 | -245 | |
| +/- 5V | -5.165 | 5.166 | DAC3to DAC3_RFB1_X2 | 0x011 | 0 | -495 | ||
| 10V | -0.165 | 10.163 | DAC3to DAC3_RFB1_X2 | 0x010 | 0 | 495 | ||
| 5V | -0.078 | 5.077 | DAC3 to DAC3_RFB1_X1 | 0x001 | 0 | 0 | ||
| 2.5V | -0.198 | 2.701 | DAC3 to DAC3_RFB1_X1 | 0x000 | 3 | -48 | ||
Table 4: AD3552R Connections for Output Configuration
The AFE board connector provides an input/output interface to the EVAL-CN0585-FMCZ board. The interface provides connections to the analog IO, ADC/DAC gain settings, GPIO, I2C, SPI, aux power, and four direct FMC connections to allow system flexibility interfacing with custom AFE designs that are provided by ADI or can be custom designed by the user.
The AFE board connector on the EVAL-CN0585-FMCZ board is a Samtec High-Density socket connector.
FMC LPC Connector Pinout for LLDK Board(Rev B)
FMC LPC connector routes the data acquired by the ADAQ23876 to FPGA and transfers the data from FPGA to AD3552R DAC.
Figure 5. FMC LPC Connector Pinout
LED Indicators
Once the board is connected to the host, and power is delivered, the green LED DS1 should be on.
Power Supply Considerations and Configuration
The Rev. B of the EVAL-CN0585-FMCZ board is powered through the USB-C connector of the board.
The board can also be powered from the FMC connector by adding resistor R9 and removing resistor R10, but it is not recommended as the current consumption exceeds the FMC standard current limit.
System Setup Using a ZedBoard
The EVAL-CN0585-FMCZ is fully supported using a ZedBoard.
Demo Requirements
Figure 6. EVAL-CN0585-FMCZ connected to EVAL-CN0584-EBZ
The following is a list of items needed to replicate this demo.
- Hardware
- ZedBoard Rev D or later board
- 12Vdc, 3A power supply
- 16GB (or larger) Class 10 (or faster) micro-SD card (included in the box)
- USB-C power source (included in the box)
- Micro-USB cable
- Ethernet cable
- User interface setup (choose one):
- HDMI monitor, keyboard, and mouse plugged directly into the ZedBoard
- Host Windows/Linux/Mac computer on the same network as the ZedBoard
- Software
- Host PC (Windows or Linux)
- A UART terminal (Putty/Tera Term/Minicom, etc.), Baud rate 115200 (8N1)
- IIO Oscilloscope
Loading Image on SD Card
The box includes a pre-programmed SD card. You can skip the steps in this section and go to the Setting up the Hardware section if using this provided card.
To boot the ZedBoard and control the EVAL-CN0585-FMCZ, you will need to install ADI Kuiper Linux on an SD card. Complete instructions, including where to download the SD card image, how to write it to the SD card, and how to configure the system are provided on the Kuiper Linux page.
Configuring the SD Card
Follow the configuration procedure under Configuring the SD Card for FPGA Projects on the Kuiper Linux page. Copy the following files onto the boot directory to configure the SD card:
- uImage file for Zynq
- BOOT.BIN specific to your EVAL-CN0585-FMCZ + ZedBoard
- devicetree.dtb devicetree for Zynq specific to your EVAL-CN0585-FMCZ + ZedBoard.The device tree describes the following devices:
- one-bit-adc-dac – controls the MAX7301
- axi_pwm_gen – generates the CNV signal for analog-to-digital converters
- ref_clk – generates the sample clock for ADAQ23876 devices and the reference clock for AD3552R devices
- rx_dma – controls the DMA for RX path
- Ltc2387 – controls ADAQ23876 devices
- qspi0 – controls the SPI devices that are connected to the PL SPI IP
- dac0_tx_dma - controls the DMA for the first AD3552R device
- dac1_tx_dma - controls the DMA for the second AD3552R device
- axi_ad3552r_0 – controls the first AD3552R device
- axi_ad3552r_1 – controls the second AD3552R device
- I2c – controls devices that are connected to PL I2C IP (eeprom, eeprom2, ad7291_1)
Setting up the Hardware
You will need to:
- Get the ZedBoard.
- Insert the SD-CARD into the SD Card Interface Connector (J12).
- Connect the EVAL-CN0585-FMCZ board into the ZedBoard FMC connector.
- Connect the EVAL-CN0584-EBZ board into the EVAL-CN0585-FMCZ.
- Connect USB UART J14 (Micro USB) to your host PC.
- Plug your ethernet cable into the RJ45 ethernet connector(J11).
- Plug the Power Supply into the 12V Power ZedBoard input connector (J20) (DO NOT turn the device on).
- Plug USB-C power supply to EVAL-CN0585-FMCZ
- Set the jumpers as seen in Figure 7
Figure 7. ZedBoard Jumper Settings - Connect the DAC output connectors to the positive ADC input connectors as shown in Figure 7 using SMA cables. Terminate the negative ADC connectors with 50ohms
Figure 8. EVAL-CN0584-EBZ Loopback Connection on AFE - Turn the ZedBoard it on.
- Wait ~30 seconds for the “DONE” LED to turn blue. This is near the DISP1.The hardware set up is now complete.
Figure 9. Example System Setup
All the products described on this page include ESD (electrostatic discharge) sensitive devices. Electrostatic charges as high as 4000V readily accumulate on the human body or test equipment and can discharge without detection.
Although the boards feature ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. This includes removing static charge on external equipment, cables, or antennas before connecting to the device.
Application Software (both locally and remotely on the FPGA)
Hardware Connection
Libiio is a library used for interfacing with IIO devices and must be installed on your computer to interface with the hardware.
Download and Install the latest Libiio package on your machine.
To connect to your device, the software must be able to create a context. The context creation in the software depends on the backend used to connect to the device as well as the platform where the EVAL-CN0585-FMCZ is attached. The ZedBoard running ADI Kuiper Linux is currently the only platform supported for the CN0585.
The user needs to supply a URI which will be used in the context creation. To get the URI, use the command iio_info in the terminal. The iio_info command is a part of the libIIO package that reports all IIO attributes.Upon installation, simply enter the command on the terminal command line to access it.
For FPGA(ZedBoard) Direct Local Access:
iio_info
For Windows machine connected to an FPGA(ZedBoard):
iio_info -u ip:<ip address of your ip>
Example:
- If your ZedBoard has the IP address 169.254.92.202, you have to use iio_info -u ip::169.254.92.202 as your URI
Do note that the Windows machine and the FPGA board should be connected to the same network for the machine to detect the device.
IIO Oscilloscope
IIO Oscilloscope is a cross platform GUI application which can interface with different evaluation boards from within a Linux system.
Make sure to download/update to the latest version of IIO-Oscilloscope found on this linkhttps://github.com/analogdevicesinc/iio-oscilloscope/releases
- Once done with the installation or an update of the latest IIO-Oscilloscope, open the application. The user needs to supply a URI which will be used in the context creation of the IIO Oscilloscope. The instructions to obtain the URI can be found in the previous section.
- Press refresh to display available IIO Devices and press connect.
Figure 10. IIO Oscilloscope Connection
- After the board is connected, select the one-bit-adc-dac-device, which is the controller for the MAX7301ATL+ I/O Expander. Then configure pins values by setting the raw value to 1 for the following output voltages.
Figure 10. MAX7301ATL Output Channels Configuration
| one-bit-adc-dac device channel | Schematic PIN |
|---|---|
| Voltage0 | GPIO0_VIO |
| Voltage1 | GPIO1_VIO |
| Voltage2 | GPIO2_VIO |
| Voltage3 | GPIO3_VIO |
| Voltage4 | GPIO6_VIO |
| Voltage5 | GPIO7_VIO |
| Voltage6 | PAD_ADC0 |
| Voltage7 | PAD_ADC1 |
| Voltage8 | PAD_ADC2 |
| Voltage9 | PAD_ADC3 |
Table 5. Voltage Configuration for GPIO Pins
- Select the desired input source for both AD3552R devices axi-ad3552r-0 and axi-ad3552r-1 as dma_input.
Figure 11. AD3552R Input Source Selection in IIO Oscilloscope
Even if the input source is set to adc_input or ramp_input the steps regarding the DAC Data Manager tab have to be followed.
- Select the desired output range for both AD3552R devices.
Figure 12. AD3552R Output Range Selection in IIO Oscilloscope
Make sure you don't try to read/write the output_range attribute when the stream_status is in start_stream or start_stream_synced.
- From the DAC Data Manager Window select the output channels of the DAC and enable the cyclic buffer for each DAC.
- Load an example file from the IIO Oscilloscope/lib/osc/waveforms folder.
If the source is set as dma_input and the data from all 4 channels needs to be synchronized make sure that you press the load button for the axi-ad3552r-1 device first then for axi-ad3552r-0.
Figure 13. DAC Data Manager with Example Waves on 4 Channels
- Click on the load button.
If the source is set as dma_input and the data from all 4 channels needs to be synchronized make sure that you write the start_stream_synced for the axi-ad3552r-1 device first then for axi-ad3552r-0.
- From the debug window, select the stream_status IIO Attribute and start the stream (start_stream_synced means that all 4 channels are updated at the same time and the data streaming process waits for both DACs to be started).
Figure 14. DAC Stream Status Selection
If the source is set as dma_input and the data from all 4 channels needs to be synchronized make sure that you write the start_stream_synced for the
axi-ad3552r-1 device first then for axi-ad3552r-0.
- After the stream_status has been written and 4 channels are enabled, you should hit play button. Then data capture window can be seen like in Figure 15.
Figure 15. Captured Loopback Signal
Note that there is a phase delay between voltage0/voltage2 and voltage1/voltage3 because the DAC device channels are updated consecutively See the DAC UPDATE MODES section in AD3552R
If you intend to stop the stream transmission and start it again synchronized set the stream_status IIO Attribute to stop_stream for axi-ad3552r-1 device first then for the axi-ad3552r-0 device.
PyADI-IIO
PyADI-IIO is a Python abstraction module to simplify interaction with IIO drivers on ADI hardware. This module provides device-specific APIs built on top of the current libIIO Python bindings. These interfaces try to match the driver naming as much as possible without the need to understand the complexities of libIIO and IIO.
Follow the step-by-step procedure on how to install, configure, and set up PYADI-IIO and install the necessary packages/modules needed by referring to PyADI-IIO.
Running the example
Github link for the Python sample script: CN0585 Python Example
After installing and configuring PYADI-IIO on your machine, you are now ready to run Python script examples. In our case, run the cn0585_fmcz_example.py found in the examples folder.
D:\pyadi-iio>export PYTHONPATH=D:/pyadi-iio/ D:\pyadi-iio>python examples/cn0585_fmcz_example.py ip:your_board_ip
Press enter and you will get these readings:
$ python examples/cn0585_fmcz_example.py uri: ip:your_board_ip ############# EEPROM INFORMATION ############ read 256 bytes from /sys/devices/soc0/fpga-axi@0/41620000.i2c/i2c-1/1-0050/eeprom Date of Man : Fri Jan 20 08:11:00 2023 Manufacturer : Analog Devices Product Name : LLDK-LTC2387-AD3552R Serial Number : 56864654 Part Number : 1234 FRU File ID : 12131321 PCB Rev : VB PCB ID : HIL BOM Rev : VC Uses LVDS : Y ############################################# GPIO4_VIO state is: 0 GPIO5_VIO state is: 0 Voltage monitor values: Channel : temp0 : 49.25 Deg. C Channel : voltage0 : 2.26745605283 V Channel : voltage1 : 0.6274414057359999 V Channel : voltage2 : 2.061157224874 V Channel : voltage3 : 0.7531738275079999 V Channel : voltage4 : 2.092285154536 V Channel : voltage5 : 2.084960935792 V Channel : voltage6 : 2.2534179669039998 V Channel : voltage7 : 1.80969238133 V AXI4-Lite 0x108 register value: 0x2 AXI4-Lite 0x10c register value: 0xB Sample data min: 0 Sample data max: 65535 input_source:dac0: adc_input input_source:dac1: adc_input Maximum measured voltage 0 : 10.115187500000001 Maximum measured voltage 1 : 0.00103125 Maximum measured voltage 2 : 0.00034375000000000003 Maximum measured voltage 3 : 0.00103125 Minimum measured voltage 0: 10.107625 Minimum measured voltage 1: -0.00034375000000000003 Minimum measured voltage 2: -0.00103125 Minimum measured voltage 3: -0.00034375000000000003
The following window will pop up:
Figure 16: ADAQ23876 Channels Python Plot
If you plan to transmit multiple cycles of synchronous stream, make sure axi-ad3552r-1 is started/stopped first, then axi-ad3552r-0.
MATLAB and Simulink
Required MATLAB Add-Ons:
Github link for the Matlab sample script: CN0585StreamingTest.m
The steps described in the Analog Devices Transceiver Toolbox For MATLAB and Simulink page have to be followed to configure the Matlab/Simulink project using the MathWorks HDL Workflow Advisor.
Device Control and Data Streaming
Remote data streaming to and from hardware is made available through system object interfaces, which are unique for each component or platform. The hardware interfacing system objects provide a class to both configure a given platform and move data back and forth from the device. After running the CN0585StreamingTest.m example as described in Steps for MATLAB Configuration of CN0585, the following window will pop up:
Figure 17. ADAQ23876 Channels Matlab Plot
If you plan to transmit multiple cycles of synchronous stream, make sure axi-ad3552r-1 is started/stopped first, then axi-ad3552r-0.
Configuring Custom HDL Models Using Simulink
ZedBoard that drives CN0585 is configured with a HDL reference design which is an embedded system built around a processor core either ARM, NIOS-II, or Microblaze. A functional block diagram of the system is shown in Figure 18.
Figure 18. HDL Reference Design
The device digital interface is handled by specific device cores axi_ad35552r for the DAC path and axi_ltc2387 for the ADC path. The cores are programmable through an AXI-lite interface. HDL IP(HDL_DUT) code to be integrated in this reference design is generated using High Speed Converter Toolbox. (https://github.com/analogdevicesinc/HighSpeedConverterToolbox/). High Speed Converter Toolbox supports the IP Core generation flow from MathWorks which allows for automated integration of DSP into HDL reference designs from Analog Devices. The workflow for generating HDL_DUT codes takes Simulink subsystems, runs HDL-Coder to generate source Verilog, and then integrates that into a larger reference design. HDL_DUT Code Generation Workflow is described in configuring_lldk.pdf and HDL_DUT with Configuration Registers (Accessed over AXI-Lite Interface) Code Generation Workflow for Transmit Configuration is described in configuring_lldk_axi_lite.pdf
Schematic, PCB Layout, Bill of Materials
EVAL-CN0585-FMCZ Design & Integration Files
- Schematics
- PCB Layout
- Bill of Materials
- Allegro Project
Additional Information and Useful Links
Reference Demos & Software
Hardware Registration
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resources/eval/user-guides/circuits-from-the-lab/cn0585.1689192083.txt.gz · Last modified: 12 Jul 2023 22:01 by Rukiye Guldali