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This version (19 May 2023 16:40) was approved by Paul Pop.

AXI_AD3552R

The axi_ad3552R IP core can be used to interface the AD3552R, a low drift, ultra-fast, 16-bit accuracy, current output digital-to-analog converter (DAC) that can be configured in multiple voltage span ranges.

Features

  • AXI-based configuration
  • Vivado and Quartus compatible
  • 8b register read/write SDR/DDR
  • 16b register read/write SDR/DDR
  • data stream SDR/DDR ( clk_in/8 or clk_in/4 update rate)
  • selectable input source: DMA/ADC/TEST_RAMP
  • data out clock(SCLK) has clk_in/8 frequency when the converter is configured and clk_in/2 when the converter is in stream mode
  • the IP reference clock (clk_in) can have a maximum frequency of 132MHz
  • the IP has multiple device synchronization capability when the DMA is set as an input data source

Block Diagram

Configuration Parameters

Name Description Default Value
ID Core ID should be unique for each IP in the system 0
FPGA_TECHNOLOGY Encoded value describing the technology/generation of the FPGA device (Arria 10/7series) set automatically
FPGA_FAMILY Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT) set automatically
SPEED_GRADE Encoded value describing the FPGA's speed-grade set automatically
DEV_PACKAGE Encoded value describing the device package. The package might affect high-speed interfaces set automatically

Interface

Interface Pin Type Description
IP interface Reference clock
dac_clk input reference clock
DAC input data from the DMAC
dma_data input[31:0] data from the DMAC when input source is set to DMA_DATA
valid_in_dma input valid from the DMAC
dac_data_ready output data ready signal for the DMAC
DAC input data from an ADC
data_in_a input[15:0] data for channel 1 when input source is set to ADC_DATA
data_in_b input[15:0] data for channel 2 when input source is set to ADC_DATA
valid_in_a input valid for channel 1
valid_in_b input valid for channel 2
Synchronization signals
valid_in_dma_sec input valid from a secondary DMAC if synchronization is needed
external_sync input external synchronization flag from another axi_ad3552r IP
sync_ext_device output start_symc external device to another axi_ad3552r IP
DAC interface Quad SPI interface
dac_sclk output Serial clock.
dac_csn output Serial chip select.
sdio_o output[3:0] Serial data out to the DAC.
sdio_i input[3:0] Serial data in from the DAC.
sdio_t output I/O buffer control signal.
s axis AXI Slave Memory Map interface
s_axi_* Standard AXI Slave Memory Map interface

Detailed Architecture

Detailed Description

The top module instantiates

  • The axi_ad3552r interface module
  • The axi_ad3552r core module
  • The AXI handling interface

The axi_ad3552r_if has the state machine that controls the quad SPI interface.
The axi_ad3552r_core module instantiates 2 axi_ad3552r channel modules.

Register Map

For the AXI_AD3552R control used registers from DAC Common are:

Address Bits Name Type Default Description
DWORD BYTE
0x0011 0x0044 REG_CNTRL_1 DAC Interface Control & Status
[1] EXT_SYNC_ARM RW 0x0 Setting this bit will arm the trigger mechanism sensitive to an external sync signal. Once the external sync signal goes high it synchronizes channels within a DAC and across multiple instances. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self-clears.
0x0012 0x0048 REG_CNTRL_2 DAC Interface Control & Status
[16] SDR_DDR_N RW 0x0 Interface type (1 represents SDR, 0 represents DDR)
[14] SYMB_8_16B RW 0x0 Select the number of bits for symbol format mode (1 represents 8b, 0 represents 16b)
0x0021 0x0084 REG_DAC_CUSTOM_WR DAC Write Configuration Data
[23:0] DATA_WRITERW 0x0000 Configuration data for the AD3552R device registers. 8/16 LSB are used depending on the 8b/16b configuration.
0x0022 0x0088 REG_UI_STATUS User Interface Status
[4] IF_BUSY RO 0x0 Interface busy. If set, indicates that the quad SPI interface is busy.
0x0023 0x008c REG_DAC_CUSTOM_CTRL DAC Control Configuration Data
[31:24] ADDRESS RW 0x00 Register address when the AD3552R is configured or stream start address when the FSM is in stream state.
[1] STREAM RW 0x0 Setting this bit will trigger a stream transfer based on the SDR/DDR configuration and address.
[0] TRANSFER_DATA RW 0x0 Setting this bit will trigger a single transfer based on the SDR/DDR, 8b/16b configuration, address, and data_write.

For the AXI_AD3552R control used registers from DAC Channel are:

Address Bits Name Type Default Description
DWORD BYTE
0x0106 0x0418 REG_CHAN_CNTRL_7 DAC Channel Control & Status (channel - 0)
[3:0] DAC_DDS_SEL[3:0] RW 0x00 Select internal data sources (available only if the DAC supports it).
- 0x02: input data (DMA)
- 0x08: loopback data (ADC)
- 0x0B: 16 bit ramp
- default: input data (DMA)
0x0116 0x0458 REG_CHAN_CNTRL_7 DAC Channel Control & Status (channel - 1)
[3:0] DAC_DDS_SEL[3:0] RW 0x00 Select internal data sources (available only if the DAC supports it).
- 0x02: input data (DMA)
- 0x08: loopback data (ADC)
- 0x0B: 16 bit ramp
- default: input data (DMA)

Base (common to all cores)

Click to expand regmap

DAC Common (axi_ad)

Click to expand regmap

DAC Channel (axi_ad*)

Click to expand regmap

Design Guidelines

The control of the chip is done through the AXI_AD3552R IP.

The DAC interface must be connected to an IO buffer.

The example design uses a DMA to move the data from the memory to the CHIP quad SPI interface.

If the data needs to be processed in HDL before moving to the memory, it can be done at the output of the IP (at the system level) or inside the axi_ad3552r_if interface module (at the IP level).

The example design uses a processor to program all the registers. If no processor is available in your system, you can create your IP starting from the interface module.

Software Guidelines

References

resources/fpga/docs/axi_ad3552r.txt · Last modified: 18 May 2023 12:58 by Paul Pop