The HDL reference design is an embedded system built around a processor core either ARM, NIOS-II, or Microblaze.
A functional block diagram of the system is shown below.
The device digital interface is handled by specific device cores axi_ad35552r for the DAC path and axi_ltc2387 for the ADC path.
The cores are programmable through an AXI-lite interface.
The digital interface consists of a Quad SPI port running at 15/60MHz depending on the FSM state (control/stream) for the DAC path and 3 LVDS serial pairs for the ADC path. The clock signals are generated by the AXI_PWM_GEN and AXI_CLKGEN IP cores.
The DAC data may be sourced from an internal data generator (DDS or pattern), from the external DDR via DMA or from the ADC. The source control selection can be made by updating the REG_CHAN_CNTRL_7 (DAC Channel) register.
The ADC data is sent to DDR via DMA. The ADC PACK IP (util_cpack) allows the use of a single DMA IP core for all 4 analog-to-digital converters.
The SPI signals of the ADC are controlled by the SPI port of the ARM processor. The DAC's control is performed by the axi_ad35552r IP core.
The HDL repository, list of supported carriers, and the list of required IP cores can be found here:
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