The axi_ltc2387 IP core interfaces to the LTC2387-16 and LTC2387-18 devices. This documentation only covers the IP core and requires that one must be familiar with the device for a complete and better understanding.
More about the generic framework interfacing ADCs can be read here: axi_adc_ip, and about our architecture here.
| ||Core ID should be unique for each LTC2387 IP in the system||0|
| ||Encoded value describing the technology/generation of the FPGA device (arria 10/7series)||set automatically|
| ||Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT)||set automatically|
| ||Encoded value describing the FPGA's speed-grade||set automatically|
| ||Encoded value describing the device package. The package might affect high-speed interfaces||set automatically|
| ||The delay group name which is set for the delay controller||“adc_if_delay_group”|
| ||Can have the values 0 or 1, conditioning the instantiation of the IODELAY_CTRL primitive. You can place only one IODELAY_CTRL per I/O bank, and need to set the same IO_DELAY_GROUP for the interfaces placed in that I/O bank.||1|
| ||Reference clock frequency used for ad_data_in instances||200|
| ||If set, indicates that the logic related to the User Data Format (e.g. decimation) was not implemented. (as a result of a configuration of the IP instance)||0|
| ||Disable the Data Format control module||0|
| ||Initial delay||22|
| ||The ADC's resolution. Can be 16/18 bits.||16|
| ||The output data resolution. Can be 16/18 bits.||16|
| ||Specifies whether the two-lane output mode is activated or not. When activated, the ADC outputs two bits at the same time, on DA+/DA- and DB+/DB-. When it is low, then DB+/DB- is disabled.||1|
| || ||Delay clock input for IO_DELAY control, connect to 200MHz clock|
|LVDS ADC interface|
| || ||LVDS input clock|
| || ||Signal enabling CLK+/CLK-|
| || ||LVDS data clock input|
| || ||Serial LVDS data input|
| || ||Serial LVDS data input|
|DMA ADC interface|
| || ||Indicates valid data at the current channel|
| || ||Received data output|
| || ||Data overflow, must be connected to the DMA|
| ||Standard AXI Slave Memory Map interface|
The LVDS interface module has as inputs the LVDS signals for clock and data:
LVDS clock input; it is an echoed version of the CLK+/CLK- signal, and it's used to latch the data outputs from the chip.
Serial LVDS data inputs; DB+/- is used only when
TWOLANES parameter is active
clk_gate is enabling the CLK+/CLK- which is driven by the reference clock. It is generated by AXI_PWM_GEN.
It is 1 for the current sample that is sent. This is generated depending on
TWOLANES parameter, whether it is set or not, the output adc_data is either taken from the DA+/- port interleaved with bits from DB+/-, or it is taken only from DA+/- port.
Here it's where the expected pattern is created and checked if the data received from the DMA is the correct one (this is used for quick validation of the design).
In the case of the device with 16-bit resolution, a sign extension is done here also.