This version (10 Aug 2023 15:07) was approved by Iulia Moldovan.The Previously approved version (10 Aug 2023 15:00) is available.
Table of Contents
AD4858-FMCZ HDL Reference Design
Overview
AD4858-FMCZ board contains AD4858 chip, which is a 20-bit, low noise 8-channel simultaneous sampling successive approximation register (SAR) ADC, with buffered differential, wide common range picoamp inputs.
More about simultaneous sampling A/D converters here.
The AD4858-FMCZ supports pin-selectable SPI CMOS and LVDS serial interfaces. In CMOS mode, applications may employ between 1-8 lanes of serial output data, allowing the user to optimize bus width and data throughput. In LVDS mode, pins SDO+/-, SCKI+/- and SCKO+/- function as differential serial data input, clock output and clock input pins respectively (from the FPGA's point of view).
Supported carriers
Hardware requirements
- Signal generator
- 1x Ethernet cable
- 1x Micro-B USB cable for UART connectivity (optional)
- 1x SD card (at least 16GB); follow this guide to set up the card
Block design
Block diagram
The data path and clock domains are depicted in the following diagram:
Clock scheme
Depending on the configuration used (CMOS or LVDS), the scheme differs a little bit. See the differences between the diagrams from below.
Because of limitations from the evaluation board, we used an internal clock of the FPGA.
Therefore, the external clocks given to AXI_AD4858 IP are:
- in LVDS mode:
external_clk= 200MHz (F_CLK0)external_fast_clk= 400MHz (F_CLK1)
- in CMOS mode:
external_clk= 100MHz (F_CLK0)
About the frequency calculation for the MMCM from axi_pwm_gen
For custom systems where the AD4858 chip is used, we recommend using an external clock, and not a clock from the FPGA like it is done in this reference design.
Description of components
The AXI_AD4858 IP core contains 2 configuration modes, these being CMOS and LVDS. Depending on which of them you want to use, different files are being used (see here).
Configurations
The AD4858-FMCZ's digital interface has two serial conversion data output modes: CMOS and LVDS. Depending on which is selected at build time (see section Building the HDL project section), specific files are used for the project. They have different constraints files and different top modules.
The AD4858 chip has 3 modes of configuration regarding the packet format: 20/24/32-bit format, which is configurable at runtime.
Limitations
The period of the SCKI clock signal is limited to a minimum of 2.5ns (at most 400MHz). Having SCKI frequency constrained, the case where the conversion time is maximum (715ns) is not achievable with the 24 and 32-bit packet formats.
In other words, if you want to use the maximum conversion rate of 400MHz, then you can use only the 20-bit packet format.
IP list
CPU/Memory interconnects addresses
| Instance | Address |
|---|---|
| axi_ad4858 | 0x43C0 0000 |
| axi_pwm_gen | 0x43D0 0000 |
| ad4858_dma | 0x43E0 0000 |
| adc_clkgen | 0x4400 0000 |
Interrupts
Below are the Programmable Logic interrupts used in this project.
Building the HDL project
ADI does not distribute the bit/elf files of these projects, so they must be built from the sources available here. To get the source you must clone the HDL repository.
Then go to projects/ad4858_fmcz/zed location and run the make command by typing in your command prompt one of the following commands, depending on which configuration you want to use:
- CMOS version of the project:
make LVDS_CMOS_N=0 - LVDS version of project:
make LVDS_CMOS_N=1
Linux/Cygwin
user@analog:~$ cd hdl/projects/ad4858_fmcz/zed user@analog:~/hdl/projects/ad4858_fmcz/zed$ make LVDS_CMOS_N=0
Check this guide on how to prepare your SD card with the proper boot files.
A more comprehensive build guide can be found in the HDL User Guide.
System setup
As for the signal generator, you can use whichever Signal Generator you want.
In this setup, we chose to use M2K (with a BNC adapter board) as signal generator for channel 0, while testing the system in LVDS mode. Using Scopy, we set the amplitude, frequency, offset and phase of the generated signals.
A more comprehensive guide on how to use M2K and Scopy can be found here and here.
Resources
- 2x BNC to SMA cables
- 2x Micro-B USB cables
Connections
- AD4858-FMCZ connected to FMC port of Zedboard
- M2K connected to PC using Micro-B USB cable
- 2x BNC to SMA cables connected from SMA0+/- (AD4858-FMCZ) to W1/W2 (BNC adapter board)
- 1x Micro-B USB for M2K connectivity to the PC
- 1x Micro-B USB for UART on Zedboard
Resources
More information
- AD4858 chip datasheet
- AXI_AD4858 IP wiki documentation
- AXI_PWM_GEN wiki documentation
- AXI_CLKGEN wiki documentation
- High-Speed DMA Controller Peripheral wiki documentation
- UTIL_CPACK2 wiki documentation
- How to prepare an SD card with boot files
- ADI HDL architecture wiki page
Support
Analog Devices will provide limited online support for anyone using the reference design with Analog Devices components via the EngineerZone FPGA reference designs forum.
It should be noted, that the older the tools' versions and release branches are, the lower the chances to receive support from ADI engineers.
resources/eval/user-guides/ad4858_fmcz/ad4858_fmcz_hdl.txt · Last modified: 10 Aug 2023 15:06 by Iulia Moldovan