AD4858-FMCZ board contains AD4858 chip, which is a 20-bit, low noise 8-channel simultaneous sampling successive approximation register (SAR) ADC, with buffered differential, wide common range picoamp inputs.
More about simultaneous sampling A/D converters here.
The AD4858-FMCZ supports pin-selectable SPI CMOS and LVDS serial interfaces. In CMOS mode, applications may employ between 1-8 lanes of serial output data, allowing the user to optimize bus width and data throughput. In LVDS mode, pins SDO+/-, SCKI+/- and SCKO+/- function as differential serial data input, clock output and clock input pins respectively (from the FPGA's point of view).
The data path and clock domains are depicted in the following diagram:
Depending on the configuration used (CMOS or LVDS), the scheme differs a little bit. See the differences between the diagrams from below.
Because of limitations from the evaluation board, we used an internal clock of the FPGA.
Therefore, the external clocks given to AXI_AD4858 IP are:
external_clk= 200MHz (F_CLK0)
external_fast_clk= 400MHz (F_CLK1)
external_clk= 100MHz (F_CLK0)
For custom systems where the AD4858 chip is used, we recommend using an external clock, and not a clock from the FPGA like it is done in this reference design.
The AD4858-FMCZ's digital interface has two serial conversion data output modes: CMOS and LVDS. Depending on which is selected at build time (see section Building the HDL project section), specific files are used for the project. They have different constraints files and different top modules.
The AD4858 chip has 3 modes of configuration regarding the packet format: 20/24/32-bit format, which is configurable at runtime.
The period of the SCKI clock signal is limited to a minimum of 2.5ns (at most 400MHz). Having SCKI frequency constrained, the case where the conversion time is maximum (715ns) is not achievable with the 24 and 32-bit packet formats.
In other words, if you want to use the maximum conversion rate of 400MHz, then you can use only the 20-bit packet format.
Below are the Programmable Logic interrupts used in this project.
Then go to projects/ad4858_fmcz/zed location and run the make command by typing in your command prompt one of the following commands, depending on which configuration you want to use:
user@analog:~$ cd hdl/projects/ad4858_fmcz/zed user@analog:~/hdl/projects/ad4858_fmcz/zed$ make LVDS_CMOS_N=0
As for the signal generator, you can use whichever Signal Generator you want.
In this setup, we chose to use M2K (with a BNC adapter board) as signal generator for channel 0, while testing the system in LVDS mode. Using Scopy, we set the amplitude, frequency, offset and phase of the generated signals.
Analog Devices will provide limited online support for anyone using the reference design with Analog Devices components via the EngineerZone FPGA reference designs forum.
It should be noted, that the older the tools' versions and release branches are, the lower the chances to receive support from ADI engineers.