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This version (07 Jul 2017 15:05) was approved by CsomI.The Previously approved version (07 Jul 2017 13:20) is available.Diff

AXI_CLKGEN IP core

The axi_clkgen IP core is a software programmable clock generator.

Block Diagram


The top module, axi_clkgen, instantiates a mcm wrapper, the CLKGEN register map and the AXI handling interface.

The ad_mmcm_drp is a wrapper over MMCM, which can instantiate a Virtex 6 MMCM or 7 Series MMCM. Detailed information regarding the 7 Series MMCM can be found in Xilinx UG472 and UG953.

The register map allows resetting the MMCM, changing the clock source, checking the status of the MMCM lock and controlling the DRP interface.

Configuration Parameter

Name Description Default Value
ID Core ID should be unique for each IP in the system 0
DEVICE_TYPE 7 Series (0) or Virtex 6 (1) device 0
CLKIN_PERIOD Default clock period for CLKIN1 5.0
CLKIN2_PERIOD Default clock period for CLKIN2 5.0
VCO_DIV DIVCLK_DIVIDE MMCM parameter 11
VCO_MUL CLKFBOUT_MULT_F MMCM parameter
CLK0_DIV CLKOUT0_DIVIDE_F MMCM parameter
CLK0_PHASE CLKOUT0_PHASE MMCM parameter 0.000
CLK1_DIV CLKOUT1_DIVIDE MMCM parameter 6
CLK1_PHASE CLKOUT1_PHASE MMCM parameter 0.000

Signal and Interface Pins

Interface Pin Type Description
Clocks Input and output clocks
clk input Reference clock 1
clk2 input Reference clock 2
clk_0 output Output clock 0
clk_1 output Output clock 1
s axi AXI Slave Memory Map interface

Register Map

Base (common to all cores)

Click to expand regmap

Clock Generator (axi_clkgen)

Click to expand regmap

References

resources/fpga/docs/axi_clkgen.txt · Last modified: 07 Jul 2017 15:04 by CsomI