All the ADI IP cores contains multiple AXI register map modules, which control a well specified part of the IP. To avoid complicated interconnections inside the IP, using the up_axi.v module, the AXI Memory Mapped interface is converted into a so called Microprocessor interface or uP interface. This interface has an independent write and read channel, and each channel contains an address bus, a data bus, a request (driven by master) and an acknowledge (driven by slave) control signals. All the uP interface signals names have a up_ prefix, this differentiate themselves clearly from other internal signals.
|Clock and reset|
| || ||Clock signal, should be connected to s_axi_aclk|
| || ||An active low reset, should be connected to s_axi_aresetn|
| || ||Read request from the processor|
| || ||Read acknowledge from the core|
| || ||Read address defined by the processor|
| || ||Read data, delivered by the core|
| || ||Write request from the processor|
| || ||Write acknowledge from the core|
| || ||Write address defined by the processor|
| || ||Write data defined by the processor|
Note: The directions of the signals are defined from the masters (microprocessor) perspective.
The following timing diagram illustrates the signals and functionality of the interface. It show a register write access and two consecutive register read access.