This is an old revision of the document!
AXI_CLKGEN IP core
The axi_clkgen IP core is a software programmable clock generator.
Block Diagram
The top module, axi_clkgen, instantiates a mcm wrapper, the CLKGEN register map and the AXI handling interface.
The ad_mmcm_drp is a wrapper over MMCM, which can instantiate a Virtex 6 MMCM or 7 Series MMCM. Detailed information regarding the 7 Series MMCM can be found in Xilinx UG472 and UG953.
The register map allows resetting the MMCM, changing the clock source, checking the status of the MMCM lock and controlling the DRP interface.
Configuration Parameter
| Name | Description | Default Value |
ID | Core ID should be unique for each IP in the system | 0 |
DEVICE_TYPE | 7 Series (0) or Virtex 6 (1) device | 0 |
CLKIN_PERIOD | Default clock period for CLKIN1 | 5.0 |
CLKIN2_PERIOD | Default clock period for CLKIN2 | 5.0 |
VCO_DIV | DIVCLK_DIVIDE MMCM parameter | 11 |
VCO_MUL | CLKFBOUT_MULT_F MMCM parameter | |
CLK0_DIV | CLKOUT0_DIVIDE_F MMCM parameter | |
CLK0_PHASE | CLKOUT0_PHASE MMCM parameter | 0.000 |
CLK1_DIV | CLKOUT1_DIVIDE MMCM parameter | 6 |
CLK1_PHASE | CLKOUT1_PHASE MMCM parameter | 0.000 |
Signal and Interface Pins
| Interface | Pin | Type | Description |
Clocks | Input and output clocks |
| | clk | input | Reference clock 1 |
| | clk2 | input | Reference clock 2 |
| | clk_0 | output | Output clock 0 |
| | clk_1 | output | Output clock 1 |
s axi | AXI Slave Memory Map interface |
Register Map
Base (common to all cores)
Click to expand regmap
| Address | Bits | Name | Type | Default | Description |
| DWORD | BYTE |
| 0x0000 | 0x0000 | REG_VERSION | Version and Scratch Registers |
| | | [31:0] | VERSION[31:0] | RO | 0x00000000 | Version number. Unique to all cores. |
| 0x0001 | 0x0004 | REG_ID | Version and Scratch Registers |
| | | [31:0] | ID[31:0] | RO | 0x00000000 | Instance identifier number. |
| 0x0002 | 0x0008 | REG_SCRATCH | Version and Scratch Registers |
| | | [31:0] | SCRATCH[31:0] | RW | 0x00000000 | Scratch register. |
| 0x0003 | 0x000c | REG_CONFIG | Version and Scratch Registers |
| | | [0] | IQCORRECTION_DISABLE | RO | 0x0 | If set, indicates that the IQ Correction module was not implemented. (as a result of a configuration of the IP instance) |
| [1] | DCFILTER_DISABLE | RO | 0x0 | If set, indicates that the DC Filter module was not implemented. (as a result of a configuration of the IP instance) |
| [2] | DATAFORMAT_DISABLE | RO | 0x0 | If set, indicates that the Data Format module was not implemented. (as a result of a configuration of the IP instance) |
| [3] | USERPORTS_DISABLE | RO | 0x0 | If set, indicates that the logic related to the User Data Format (e.g. decimation) was not implemented. (as a result of a configuration of the IP instance) |
| [4] | MODE_1R1T | RO | 0x0 | If set, indicates that the core was implemented in 1 channel mode. (e.g. refer to AD9361 data sheet) |
| [5] | DELAY_CONTROL_DISABLE | RO | 0x0 | If set, indicates that the delay control is disabled for this IP. (as a result of a configuration of the IP instance) |
| [6] | DDS_DISABLE | RO | 0x0 | If set, indicates that the DDS is disabled for this IP. (as a result of a configuration of the IP instance) |
| [7] | CMOS_OR_LVDS_N | RO | 0x0 | CMOS or LVDS mode is used for the interface. (as a result of a configuration of the IP instance) |
| [8] | PPS_RECEIVER_ENABLE | RO | 0x0 | If set, indicates the PPS receiver is enabled. (as a result of a configuration of the IP instance) |
| [9] | SCALECORRECTION_ONLY | RO | 0x0 | If set, indicates that the IQ Correction module implements only scale correction. IQ correction must be enabled. (as a result of a configuration of the IP instance) |
| [12] | EXT_SYNC | RO | 0x0 | If set the transport layer cores (ADC/DAC) have implemented the support for external synchronization signal. |
| [13] | RD_RAW_DATA | RO | 0x0 | If set, the ADC has the capability to read raw data in register REG_CHAN_RAW_DATA from adc_channel. |
| 0x0004 | 0x0010 | REG_PPS_IRQ_MASK | PPS Interrupt mask |
| | | [0] | PPS_IRQ_MASK | RW | 0x1 | Mask bit for the 1PPS receiver interrupt |
| 0x0007 | 0x001c | REG_FPGA_INFO | FPGA device information Intel encoded values Xilinx encoded values |
| | | [31:24] | FPGA_TECHNOLOGY | RO | 0x0 | Encoded value describing the technology/generation of the FPGA device (arria 10/7series) |
| [23:16] | FPGA_FAMILY | RO | 0x0 | Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT or zynq, kintex, virtex) |
| [15:8] | SPEED_GRADE | RO | 0x0 | Encoded value describing the FPGA's speed-grade |
| [7:0] | DEV_PACKAGE | RO | 0x0 | Encoded value describing the device package. The package might affect high-speed interfaces |
| Tue Mar 14 10:17:59 2023 | |
Clock Generator (axi_clkgen)
Click to expand regmap
| Address | Bits | Name | Type | Default | Description |
| DWORD | BYTE |
| 0x0010 | 0x0040 | REG_RSTN | Interface Control & Status |
| | | [1] | MMCM_RSTN | RW | 0x0 | MMCM reset (required for DRP access). Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core. |
| [0] | RSTN | RW | 0x0 | Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core. |
| 0x0011 | 0x0044 | REG_CLK_SEL | Clock Select |
| | | [0] | CLK_SEL | RW | 0x0 | Select betwen CLKIN1 (0x0) or CLKIN2 (0x1) input clock for the MMCM |
| 0x0017 | 0x005c | REG_MMCM_STATUS | MMCM Status |
| | | [0] | MMCM_LOCKED | RO | 0x0 | LOCKED status of the MMCM |
| 0x001c | 0x0070 | REG_DRP_CNTRL | ADC Interface Control & Status |
| | | [28] | DRP_RWN | RW | 0x0 | DRP read (0x1) or write (0x0) select (does not include GTX lanes). |
| [27:16] | DRP_ADDRESS[11:0] | RW | 0x000 | DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes). |
| [15:0] | DRP_WDATA[15:0] | RW | 0x0000 | DRP write data (does not include GTX lanes). |
| 0x001d | 0x0074 | REG_DRP_STATUS | MMCM Status |
| | | [17] | MMCM_LOCKED | RO | 0x0 | LOCKED status of the MMCM |
| [16] | DRP_STATUS | RO | 0x0 | If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes). |
| [15:0] | DRP_RDATA | RO | 0x0000 | DRP read data (does not include GTX lanes). |
| 0x0050 | 0x0140 | REG_FPGA_VOLTAGE | FPGA device voltage information |
| | | [15:0] | FPGA_VOLTAGE | RO | 0x0 | The voltage of the FPGA device in mv |
| Tue Mar 14 10:17:59 2023 | |
References
This version (11 Oct 2021 15:53) was approved by Adrian Costina.The Previously approved version (14 Jan 2021 05:24) is available.