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This version (29 Sep 2022 14:25) was approved by Iulia Moldovan.The Previously approved version (27 Sep 2022 15:03) is available.Diff

HDL Architecture

Every HDL design of a reference project can be divided into two subsystems:

  • Base design — description of what the carrier contains:
    • an embedded processor - soft or hard
    • all the peripheral IPs (that are necessary to run a Linux distribution on the system)
    • these designs are specific to each carrier, making them carrier dependent
    • it describes part of the system_wrapper module
    • located in /hdl/projects/common/*; one for each carrier
  • Board design — description of what the board attached to the carrier contains:
    • all the necessary IPs needed to support the board
    • these designs are common to all carriers, making them carrier independent
    • it describes part of the system_wrapper module
    • located in /hdl/projects/$project_name/common/*bd.tcl
How they're instantiated:

In case of a project, inside the system_bd.tcl file, we have to source the base design first, then the board design.

Example

Take FMCOMMS2 with Zedboard, the system_bd.tcl will look like the following:

source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl
source ../common/fmcomms2_bd.tcl

Typical project diagram

HDL overall system


Base Design

The base design contains all the I/O peripheral and memory interfaces and processing components, which are necessary for a fully functional Linux system. The majority of these components are Intel and Xilinx IP cores.

Typically, this contains:

  • Microprocessor
  • Memory interface controller
  • Peripheral interfaces

Microprocessor

In our designs, we use only two types:

Intel Xilinx
SoC FPGA SoC FPGA ACAP
HPS NIOS II PS7 PS8 MicroBlaze™ Versal

Worth mentioning in case of SoCs, the Hard Processor System (HPS) or Processing System 7/8 (PS7/8) do not contain just the dual-core ARM® Cortex® - A9 MPCore™ processor, they also have other integrated peripherals and memory interfaces. For more information please visit the manufacturer's website, listed in the table above.

Memory Interface Controller

In almost all cases, the carrier board is not made and designed by Analog Devices, so the external memory solution of the system is given. Meaning we can not support, modify or alter this important part of the system, in several cases we even have system limitations because of it (e.g. the memory interface is not fast enough to handle the required data throughput).

Under the two links below the user can find the landing page of the available memory solutions for both Altera and Xilinx:

Peripheral Interfaces

These interfaces are used to control external peripherals located on the prototyping board or the FMC IO board.
In HDL, these ports are named slightly different than how they're in the documentations. Thus, to make it easier for beginners, here you have the naming of the ports depending on the microprocessor used.

SPI

In general, the base system has two Serial Peripheral Interfaces, which are used as a control interface for FMC/HSMC devices. These SPI interfaces are controlled by the integrated SPI controller of the Hard Processor System (HPS) or Processing System 7/8 (PS7/8) or an Intel or Xilinx SPI controller core.

I2C/I2S/SPDIF

A couple of carrier boards require these standard interfaces for different purposes, for example, a configuration interface for an audio peripheral device. These peripherals do not necessarily have vital roles in the reference design, it's more like a generic goal to support all the provided peripherals of the carrier board.

HDMI

There is HDMI support for all the carriers which are using the ADV7511 as HDMI transmitter. The HDMI transmitter core can be found here.

GPIOs

The general rule of thumb is to define 64 GPIO pins for the base design:

  • bits [31: 0] always belong to the carrier board;
  • bits [63:32] will be assigned to switches, buttons and/or LEDs, which can be found on the FMC board.

When some of these GPIOs are not used, the input pins should have the output pins driven to them, so that Vivado will not complain about inputs not being assigned to.

Depending on the processor type, add these values to the GPIO number from the HDL project to obtain the final number used in software:

  • PS7 EMIO offset = 54
  • PS8 EMIO offset = 78

Connectivity

  • Ethernet
  • USB OTG

These interfaces designs are borrowed from the golden reference design of the board.

Interrupts

When developing the Linux software parts for an HDL project, the interrupts number to the PS have a different number in the software side.

Not a rule, but in our designs we preffer to use firstly the interrupts from 15 and to go down to 0. Be careful when assigning one, because it might be used in the base design of the carrier!

Always check which are used (in /projects/common/$carrier/$carrier_system_bd.tcl)

Click here to see the interrupts table


Board design

Board capabilities - Xilinx platforms

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Board capabilities

Board capabilities - Xilinx

Board name Boots from FMC connector 1 FMC connector 2
AC701 JTAG HPC (2 GTP @ 6.6Gbps)
Cora Z7-07S SD card
KC705 JTAG HPC (4 GTX @ 10.3125 Gbps) LPC (1 GTX @ 10.3125 Gbps)
KCU105 JTAG HPC (8 GTH @ 16.3 Gbps) LPC (1 GTH @ 16.3 Gbps)
Microzed JTAG
VC707 JTAG HPC (8 GTX @ 12.5 Gbps) HPC (8 GTX @ 12.5 Gbps)
VC709 JTAG HPC (10 GTH @ 13.1 Gbps)
VCK190 SD card FMC+ (12 GTY @ 28.21 Gbps) FMC+ (12 GTY @ 28.21 Gbps)
VCU118 JTAG FMC+ (24 GTY @ 28.21 Gbps) LPC
VCU128 JTAG FMC+ (24 GTY @ 28.21 Gbps)
VMK180 SD card FMC+ (12 GTY @ 28.21 Gbps) FMC+ (12 GTY @ 28.21 Gbps)
ZC702 SD card LPC LPC
ZC706 SD card HPC (8 GTX @ 10.3125 Gbps) LPC (1 GTX @ 10.3125 Gbps)
ZCU102 SD card HPC (8 GTH @ 16.3 Gbps) HPC (8 GTH @ 16.3 Gbps)
Zedboard SD card LPC
VADJ values
Board name FMC 1 FMC 2 Family
AC701 3.3V/*2.5V/1.8V Artix-7
Cora Z7-07S Zynq-7000
KC705 3.3V/*2.5V/1.8V 3.3V/*2.5V/1.8V Kintex-7
KCU105 *1.8V/1.5V/1.2V *1.8V/1.5V/1.2V Kintex UltraScale
Microzed Zynq-7000
VC707 *1.8V/1.5V/1.2V *1.8V/1.5V/1.2V Virtex-7
VC709 *1.8V Virtex-7
VCK190 *1.5V/1.2V *1.5V/1.2V Versal
VCU118 *1.8V/1.5V/1.2V *1.8V/1.5V/1.2V Virtex UltraScale+
VCU128 *1.8V/1.5V/1.2V Virtex UltraScale+
VMK180 *1.5V/1.2V *1.5V/1.2V Versal
ZC702 3.3V/*2.5V/1.8V 3.3V/*2.5V/1.8V Zynq-7000
ZC706 3.3V/*2.5V/1.8V 3.3V/*2.5V/1.8V Zynq-7000
ZCU102 *1.8V/1.5V/1.2V *1.8V/1.5V/1.2V Zynq UltraScale+ MP
Zedboard 3.3V/2.5V/*1.8V Zynq-7000

(* bold) = default VADJ
FMC1 & FMC2 columns → depending on the power supply of the device connected to the FMC, the custom VADJ will have the value supported by both the carrier and the device(s)

Board capabilities - Intel platforms

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Board capabilities

Board capabilities - Intel

Board name FMC connector 1 FMC connector 2
A10GX LPC () HPC (8 x 17.4 Gbps)
A10SOC HPC (8) LPC (8)
Stratix10SoC FMC+ (24 @ 28.3 Gbps) FMC+ (24 @ 28.3 Gbps)
VADJ values
Board name FMC 1 FMC 2
A10GX *1.8V/1.5V/1.35V/1.2V *1.8V/1.5V/1.35V/1.2V
A10SOC *1.8V/1.5V/1.35V/1.25V/1.2V/1.1V *1.8V/1.5V/1.35V/1.2V/1.1V
Stratix10SoC *3.3V/1.8V/1.2V *3.3V/1.8V/1.2V

(* bold) = default VADJ
FMC1 & FMC2 columns → depending on the power supply of the device connected to the FMC, the custom VADJ will have the value supported by both the carrier and the device(s)


File structure of a project

In /projects/common/$carrier_name/ you can find templates for the system_top.v, Makefile, etc. to help you when creating a new project.

Project files for Xilinx boards

A project for a Xilinx FPGA board should contain the following files:

  • Makefile — auto-generated file; contains all the IP dependencies needed for the project to be built
  • system_project.tcl — script that creates the actual Vivado project and runs the synthesis/implementation of the design
  • system_bd.tcl — sources the base design first, then the board design, and afterwards it contains all the IP instances and connections that must be added on top of the sourced files, to complete the design of the project (these are specific to the combination of this carrier and board)
  • system_constr.xdc — constraints file of the design; it’s the connection between the physical pins of the FPGA that you want to use and the HDL code that describes the behavior; here you define the FMC I/O pins, board-specific clock signals, timing constraints, etc. The constraints specific to the carrier are imported in the system_project.tcl file
  • system_top.v — contains everything about the HDL part of the project; it instantiates the system_wrapper module, IO buffers, I/ODDRs, modules that transform signals from LVDS to single-ended, etc. The I/O ports of this Verilog module will be connected to actual I/O pads of the FPGA.
    • system_wrapper — tool generated file and can be found at <project_name>.srcs/sources_1/bd/system/hdl/system_wrapper.v
      • the I/O ports of this module are declared in either system_bd.tcl or in the board design file
      • this can be visualized in Vivado at the Block Design section
      • the base design, board design and system_bd.tcl describe this module, making the connections between the instantiated IPs

Project files for Intel boards

A project for an Intel FPGA board should contain the following files:

  • Makefile — auto-generated file; contains all the IP dependencies needed for the project to be built
  • system_project.tcl — script that creates the actual Quartus project and runs the synthesis/implementation of the design. It also contains the I/O definitions for the interfaces between the board and the FPGA
  • system_qsys.tcl — also called platform designer; sources the base design first, then the board design, and afterwards it contains all the IP instances and connections that must be added on top of the sourced files, to complete the design of the project (these are specific to the combination of this carrier and board)
  • system_constr.sdc — contains clock definitions and other path constraints
  • system_top.v — contains everything about the HDL part of the project; it instantiates the system_wrapper module, IO buffers, I/ODDRs, modules that transform signals from LVDS to single-ended, etc. The I/O ports of this Verilog module will be connected to actual I/O pads of the FPGA
Examples

Some carriers have a different name for these files, for example A10SoC has constraints file for both PL side and PS side:

  • a10soc_plddr4_assign.tcl — constraints file for the PL
  • a10soc_system_assign.tcl — constraints file for the PS

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resources/fpga/docs/arch.txt · Last modified: 29 Sep 2022 14:25 by Iulia Moldovan