Every HDL design of a reference project can be divided into two subsystems:
In case of a project, inside the system_bd.tcl file, we have to source the base design first, then the board design.
Take FMCOMMS2 with Zedboard, the system_bd.tcl will look like the following:
source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl source ../common/fmcomms2_bd.tcl
The base design contains all the I/O peripheral and memory interfaces and processing components, which are necessary for a fully functional Linux system. The majority of these components are Intel and Xilinx IP cores.
Typically, this contains:
In our designs, we use only two types:
Worth mentioning in case of SoCs, the Hard Processor System (HPS) or Processing System 7/8 (PS7/8) do not contain just the dual-core ARM® Cortex® - A9 MPCore™ processor, they also have other integrated peripherals and memory interfaces. For more information please visit the manufacturer's website, listed in the table above.
In almost all cases, the carrier board is not made and designed by Analog Devices, so the external memory solution of the system is given. Meaning we can not support, modify or alter this important part of the system, in several cases we even have system limitations because of it (e.g. the memory interface is not fast enough to handle the required data throughput).
Under the two links below the user can find the landing page of the available memory solutions for both Altera and Xilinx:
These interfaces are used to control external peripherals located on the prototyping board or the FMC IO board.
In HDL, these ports are named slightly different than how they're in the documentations. Thus, to make it easier for beginners, here you have the naming of the ports depending on the microprocessor used.
In general, the base system has two Serial Peripheral Interfaces, which are used as a control interface for FMC/HSMC devices. These SPI interfaces are controlled by the integrated SPI controller of the Hard Processor System (HPS) or Processing System 7/8 (PS7/8) or an Intel or Xilinx SPI controller core.
A couple of carrier boards require these standard interfaces for different purposes, for example, a configuration interface for an audio peripheral device. These peripherals do not necessarily have vital roles in the reference design, it's more like a generic goal to support all the provided peripherals of the carrier board.
There is HDMI support for all the carriers which are using the ADV7511 as HDMI transmitter. The HDMI transmitter core can be found here.
The general rule of thumb is to define 64 GPIO pins for the base design:
When some of these GPIOs are not used, the input pins should have the output pins driven to them, so that Vivado will not complain about inputs not being assigned to.
Depending on the processor type, add these values to the GPIO number from the HDL project to obtain the final number used in software:
These interfaces designs are borrowed from the golden reference design of the board.
When developing the Linux software parts for an HDL project, the interrupts number to the PS have a different number in the software side.
Not a rule, but in our designs we preffer to use firstly the interrupts from 15 and to go down to 0. Be careful when assigning one, because it might be used in the base design of the carrier!
Always check which are used (in /projects/common/$carrier/$carrier_system_bd.tcl)
A project for a Xilinx FPGA board should contain the following files:
A project for an Intel FPGA board should contain the following files:
Some carriers have a different name for these files, for example A10SoC has constraints file for both PL side and PS side: