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This version (24 Feb 2022 15:06) was approved by Adrian Costina.The Previously approved version (13 Oct 2021 10:07) is available.Diff

AXI_PWM_GEN

The axi_pwm_gen core is used to generate a maximum of four configurable signals(pwms). The pulses are generated according to the state of a counter, one counter for each pulse.

Features

  1. up to four configurable signals(period, width, offset)
  2. external synchronization
  3. external clock

The offset feature will synchronize counters 0, 1, 2 and 3 to an offset counter.

The axi_pwm_gen core can be synchronized by an external signal. The offset counter will wait for a high to low transition of the synchronization pulse. If another synchronization is needed, the external_sync signal should be set high and the load_config should be toggled(by register write). This will cause the counters to wait for another external_sync high to low transition. To disable a pwm, write 0 to it's period register.

Block Diagram

Configuration Parameters

Name Description Default Value
ID Core ID should be unique for each IP in the system 0
ASYNC_CLK_EN Use external clock, asynchronous to s_axi_aclk 1
N_PWMS Number of pulses/pwms 1
PWM_EXT_SYNC PWM offset counter uses external sync 0
EXT_ASYNC_SYNC The external sync for pulse 0 is asynchronous 0
PULSE_0_WIDTH Pulse 0 width (number of clk cycles) 7
PULSE_1_WIDTH Pulse 1 width (number of clk cycles) 7
PULSE_2_WIDTH Pulse 2 width (number of clk cycles) 7
PULSE_3_WIDTH Pulse 3 width (number of clk cycles) 7
PULSE_0_PERIOD Pulse 0 period (number of clk cycles) 10
PULSE_1_PERIOD Pulse 1 period (number of clk cycles) 10
PULSE_2_PERIOD Pulse 2 period (number of clk cycles) 10
PULSE_3_PERIOD Pulse 3 period (number of clk cycles) 10
PULSE_0_OFFSET Pulse 1 period (number of clk cycles) 0
PULSE_1_OFFSET Pulse 1 period (number of clk cycles) 0
PULSE_2_OFFSET Pulse 2 period (number of clk cycles) 0
PULSE_3_OFFSET Pulse 3 period (number of clk cycles) 0

Signal and Interface Pins

Interface Pin Type Description
External clock Clock signal
ext_clk input Input clock
External sync external sync signal
external_sync, input Synchronize pulses to an external signal
PWM pwm signals
pwm_0 output [1] Output pwm 0
pwm_1 output [1] Output pwm 1
pwm_2 output [1] Output pwm 2
pwm_3 output [1] Output pwm 3
s_axi AXI Memory Map interface

Functionality

The axi_pwm_gen offers the possibility of four output signals(pwms). Pulse 0, 1, 2 and 3 can have offsets in referenced to pwm counter.

The pulse generator is based on incrementing counters. In a pulse period, the first interval of the signal, until the level transition, the signal level is high(pulse_width) and the second interval is low(pulse_period-pulse_width).

By default, all counters start at the same time. When a different phase(delay) is needed between the pulses, the offset value is calculated in number of clock cycles:

The below timing diagram, shows the external_sync functionality.

The below timing diagram, shows the load_config functionality. All four pulses are active and all four pulses have the same period.

Register Map

Register map

The register map of the core contains instances of several generic register maps like ADC common, ADC channel, DAC common, DAC channel etc. The following table presents the base addresses of each instance, after that can be found the detailed description of each generic register map. The absolute address of a register should be calculated by adding the instance base address to the registers relative address.

PWM Generator (axi_pwm_gen)

Click to expand regmap

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resources/fpga/docs/axi_pwm_gen.txt · Last modified: 24 Feb 2022 15:03 by Iulia Moldovan