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This version (16 Apr 2019 10:39) was approved by lnagy.The Previously approved version (19 Feb 2019 16:06) is available.Diff

AXI_AD9371

The axi_ad9371 IP core interfaces to the AD9371 device. This documentation only covers the IP core and requires that one must be familiar with the device for a complete and better understanding.

Features

  • AXI Lite control/status interface
  • Hardware and software DC filtering
  • IQ correction
  • Internal DDS
  • Receive and transmit loopback
  • Supports both Altera and Xilinx devices

Block Diagram

Functional Description

The axi_ad9371 cores architecture contains:

Interface Description

The interface module of the core is connected to the JESD204B IP core and does a simple realignment of the data stream.

Parameters

Name Description Default Value
ID Core ID should be unique for each ad9371 IP in the system 0
DEVICE_TYPE Used to select between 7 Series (0), Virtex 6 (1) or Ultrascale (2) for Xilinx devices 0
ADC_DATAPATH_DISABLE Disable the receive data path modules. 0
DAC_DATAPATH_DISABLE Disable the transmit data path modules. 0

I/O interface and signals

Interface Pin Type Description
Receive interface from JESD204B IP
adc_clk input Rx core clock from the GTs, in general clock rate is (Lane Rate)/40.
adc_rx_valid input This signal is unused; is defined just to make tools happy.
adc_rx_sof input[3:0] Frame boundary indication signals. Indicate the byte position of the first byte of a frame.
adc_rx_data input[63:0] Received data stream from the JESD204B IP.
adc_rx_ready output This signal is tied to one; is defined just to make tools happy.
Observation receive interface from JESD204B IP
adc_os_clk input Rx core clock from the GTs, in general clock rate is (Lane Rate)/40.
adc_rx_os_valid input This signal is unused; is defined just to make tools happy.
adc_rx_os_sof input[3:0] Frame boundary indication signals. Indicate the byte position of the first byte of a frame.
adc_rx_os_data input[63:0] Received data stream from the JESD204B IP.
adc_rx_os_ready output This signal is tied to one; is defined just to make tools happy.
Transmit interface to JESD204B IP
dac_clk input Tx core clock from the GTs, in general clock rate is (Lane Rate)/40.
dac_tx_valid output This signal is tied to one; is defined just to make tools happy.
dac_tx_data output[63:0] Transmitted data stream to the JESD204B IP.
dac_tx_ready input This signal is not used; is defined just to make tools happy.
Transmit master/slave
dac_sync_in input Synchronization signal of the transmit path for slave devices (ID>0)
dac_sync_out output Synchronization signal of the transmit path for master device (ID==0)
Receive FIFO interface (for DMA)
adc_enable_* output If set, the channel is enabled (one for each channel)
adc_valid_* output Indicates valid data at the current channel (one for each channel)
adc_data_* output[15:0] Received data output (one for each channel)
adc_dovf input Data overflow, must be connected to the DMA
adc_dunf input Data underflow, must be connected to the DMA
Observation FIFO interface (for DMA)
adc_os_enable_* output If set, the channel is enabled (one for each channel)
adc_os_valid_* output Indicates valid data at the current channel (one for each channel)
adc_os_data_* output[31:0] Received data output (one for each channel)
adc_os_dovf input Data overflow, must be connected to the DMA
adc_os_dunf input Data underflow, must be connected to the DMA
Transmit FIFO interface (for DMA)
dac_enable_* output If set, the channel is enabled (one for each channel)
dac_valid_* output Indicates valid data request at the current channel (one for each channel)
dac_data_* input[31:0] Transmitted data output (one for each channel)
dac_dovf input Data overflow, must be connected to the DMA
dac_dunf input Data underflow, must be connected to the DMA
AXI Slave Memory Mapped interface
s_axi_* Standard AXI Slave Memory Map interface

Register Map

The register map of the core contains instances of several generic register maps like ADC common, ADC channel, DAC common, DAC channel etc. The following table presents the base addresses of each instance, after that can be found the detailed description of each generic register map. The absolute address of a register should be calculated by adding the instance base address to the registers relative address.

Register Map base addresses for axi_ad9371

Address Name Description
DWORD BYTE
0x0000 0x0000 BASE See the Base (common to all cores) table for more detail
0x0000 0x0000 RX COMMON See the ADC Common table for more detail
0x0000 0x0000 ADC TPL See the JESD TPL table for more detail
0x0000 0x0000 RX CHANNELS See the ADC Channel table for more detail
0x1000 0x4000 TX COMMON See the DAC Common table for more detail
0x1000 0x4000 DAC TPL See the JESD TPL table for more detail
0x1000 0x4000 TX CHANNELS See the DAC Channel table for more detail
0x2000 0x8000 RX OS CHANNELS See the ADC Channel table for more detail

Base (common to all cores)

Click to expand regmap

ADC Common (axi_ad*)

Click to expand regmap

ADC Channel (axi_ad*)

Click to expand regmap

DAC Common (axi_ad*)

Click to expand regmap

DAC Channel (axi_ad*)

Click to expand regmap

JESD TPL (up_tpl_common)

Click to expand regmap

Design Guidelines

TBD

Software Guidelines

The software for this IP can be found as part of the FMCOMMS2/3/4/5 Reference Design at No-Os Software.
Linux is supported also using ADI Linux repository

References

resources/fpga/docs/axi_ad9371.txt · Last modified: 16 Apr 2019 10:32 by lnagy