The following wiki page presents a generic framework, which is used to design and develop an AXI based IP core for interfacing an ADC device with a high speed serial (JESD204B) or source synchronous parallel interface (LVDS/CMOS). This is a generic framework, there can be minor differences on each and every IP, the user should study this wiki page along with the IP's wiki page.
The main role of this page to ease the understanding of each ADC IP, and to provide a base knowledge which can be used to develop new IPs for currently unsupported devices.
The main function of an AXI ADC IP is to handle all the low level signalling, which is defined by the device's digital data interface, and to forward the received data to a more simple FIFO interface. Beside this functionality there are a few processing modules inside the data path of the core, which can be used for signal conditioning. All these processing modules are optional, the are enabled or disabled by setting the appropriate parameters. The following block diagram presents a generic AXI ADC IP cores data path.
The most important part of the core is the Receiver PHY module. This module contains all the IO primitive instantiations and all the control logic required to receive data from the device.
Currently the Receiver PHY supports several different receive interface:
All these interfaces are supported on both Altera (Intel) and Xilinx devices.
This module is perfect choice for those, who wants a HDL logic for the device interface, with a minimal resource footprint.
(1) The receive module contains just the Transport Layer of the JESD204B interface. Lower layers are implemented by other cores.
The ADC core is the top file of the IP core, the naming convention of this file is: axi_<device_name>.v . Here are instantiated all the internal module discussed above, and a wrapper module (up_axi), which converts the AXI interface into a more simplistic addressable, memory mapped interface, so called microprocessor interface or uP interface. This interface is used to interconnect the different memory mapped module pieces.
A generic AXI ADC core have at least three different interfaces:
|LVDS or CMOS RX interface|
| ||clock input||clock input|
| ||input[resolution-1:0]||parallel data input|
| ||input||frame input signal (optional/device specific)|
| ||input||over range input (optional/device specific)|
|JESD RX interface|
| ||clock input||core clock|
| ||input[3:0]||start of frame signal|
| ||input[DW-1:0]||data input; DW=32*MAX_LANE_NO|
| ||output||ready, core always ready (tied to HIGH)|
| ||input||data valid|
|Write FIFO interface|
| ||clock output||Interface's clock signal|
| ||output||Enable signal for the first channel, asserted if channel is active|
| ||output||Data valid signal for the first channel, to validate data on the bus|
| ||output[DW-1:0]||Data signal for the first channel|
| ||output||Enable signal for the channel x, asserted if channel is active|
| ||output||Data valid signal for the channel x, to validate data on the bus|
| ||output[DW-1:0]||Data signal for the channel x|
| ||input||Data overflow signal from the receiver or sink module (e.g DMA)|
| ||input||Data underflow signal from the receiver or sink module (e.g DMA)|
|AXI Memory Map Slave|
| ||Standard AXI Slave Memory Map interface for register map access|
The following block diagram presents the different register maps physical location in the core. These register maps are generic and can be found in each AXI ADC core.
The base and ADC common register map is implemented in the same verilog file. It contains registers which controls and monitors the overall core, like:
up_adc_commoninside the IP's directory.
The ADC Channel register map controls and monitors channel specific attributes. Each channel of the core has an individual channel register map. It contains all the registers, which are necessary to control and monitor the processing modules of the data path. For detailed description of the available processing modules see ADC channel section.
up_adc_channelinside the IP's directory.