The following wiki page presents a generic framework, which is used to design and develop an AXI based IP core for interfacing a Digital to Analog Converter (DAC) device with a high speed serial (JESD204B) or source synchronous parallel interface (LVDS/CMOS). This is a generic framework, there can be minor differences on each and every IP, the user should study this wiki page along with the IP's wiki page.
The main role of this page to ease the understanding of each DAC IP, and to provide a base knowledge which can be used to develop new IPs for currently unsupported devices.
The main function of an AXI DAC IP is to handle all the low level signalling, which is defined by the device's digital data interface, and to forward the received data from the DMA or any other data source to the device. Beside this functionality there are a few processing modules inside the data path of the core, which can be used for signal conditioning. All these processing modules are optional, the are enabled or disabled by setting the appropriate parameters. The following block diagram presents a generic AXI DAC IP cores data path.
The most important part of the core is the Transmit PHY module. This module contains all the IO primitive instantiations and all the control logic required to receive data from the device.
In some cases, when the IP supports multiple interface type, the name of the PHY module look like: axi_<device_name>_<interface_type>_if.v (e.g. axi_ad9361_lvds_if.v)
Currently the Transmit PHY supports two different transmit interface:
All these interfaces are supported on both Altera (Intel) and Xilinx devices.
This module is perfect choice for those, who wants a HDL logic for the device interface, with a minimal resource footprint.
(1) The transmit module contains just the Transport Layer of the JESD204B interface. Lower layers are implemented by other cores.
The DAC core is the top file of the IP core, the naming convention of this file is: axi_<device_name>.v . Here are instantiated all the internal module discussed above, and a wrapper module (up_axi), which converts the AXI interface into a more simplistic addressable, memory mapped interface, so called microprocessor interface or uP interface. This interface is used to interconnect the different memory mapped module pieces.
A generic AXI DAC core have at least three different interfaces:
|LVDS or CMOS TX interface
|clock input (device's DCO)
|clock output (device's DCI)
|parallel data output (note that multiple parallel data buses can exist)
|JESD TX interface
|core clock or device clock (must be (line clock)/40)
|data input; DW=32*MAX_LANE_NO
|Read FIFO interface
|Interface's clock signal
|Enable signal for the first channel, asserted if channel is active
|Data valid signal for the first channel, to validate data on the bus
|Data signal for the first channel
|Enable signal for the channel x, asserted if channel is active
|Data valid signal for the channel x, to validate data on the bus
|Data signal for the channel x
|Data underflow signal from the receiver or sink module (e.g DMA)
|AXI Memory Map Slave
|Standard AXI Slave Memory Map interface for register map access
The following block diagram presents the different register maps physical location in the core. These register maps are generic and can be found in each AXI DAC core.
The base and DAC common register map is implemented in the same verilog file. It contains registers which controls and monitors the overall core, like:
up_dac_common inside the IP's directory.
The DAC Channel register map controls and monitors channel specific attributes. Each channel of the core has an individual channel register map. It contains all the registers, which are necessary to control and monitor the processing modules of the data path. For detailed description of the available processing modules see DAC channel section.
up_dac_channel inside the IP's directory.