This version (20 Apr 2022 10:48) was approved by Iulia Moldovan.The Previously approved version (13 Oct 2021 09:17) is available.

AXI_AD9144 (Obsolete)

This page is kept for historical reasons. The same functionalities are implemented using the generic JESD204 TPL IPs

The axi_ad9144 IP core can be used to interface the AD9144 DAC. An AXI Memory Map interface is used for configuration. Data is sent in a format that can be transmitted by Xilinx's JESD IP.

More about the generic framework interfacing DACs can be read here: axi_dac_ip.

Features

AXI based configuration
Hardware PRBS generation
Hardware DDS generation
Xilinx Vivado compatible
Altera Quartus compatible

Block Diagram

Configuration Parameters

Name	Description	Default Value
`ID`	Core ID should be unique for each AD9144 IP in the system	0
`QUAD_OR_DUAL_N`	Selects if 4 lanes (1) or 2 lanes (0) are connected	1
`DAC_DATAPATH_DISABLE`	If set, the DDS modules are not implemented	0

Interface

Interface	Pin	Type	Description
`jesd interface`	Data to be connected to the JESD core
	`tx_clk*`	`input`	Line rate / 40
	`tx_ready*`	`input`	Not used in the IP, just for interface compatibility reasons
	`tx_data`	`output[255/127:0]`	Data to be sent to the JESD core. 256 bit wide for QUAD operation, and 128 bit for DUAL operation
	`tx_valid*`	`output`	Always set to 1, for interface compatibility reasons
`s axi`	AXI Slave Memory Map interface
`dma interface`	FIFO interface for connecting to the DMA
	`dac_clk`	`output`	Loopback of the tx_clk. Most of the modules of the core run on this clock
	`dac_valid_0`	`output`	DAC valid, used to read new data from the DMA
	`dac_enable_0`	`output`	Set when the channel is enabled, activated by software
	`dac_ddata_0`	`input[63:0]`	Data for channel 0, 4 samples
	`dac_valid_1`	`output`	DAC valid, used to read new data from the DMA
	`dac_enable_1`	`output`	Set when the channel is enabled, activated by software
	`dac_ddata_1`	`input[63:0]`	Data for channel 1, 4 samples
	`dac_valid_2`	`output`	DAC valid, used to read new data from the DMA
	`dac_enable_2`	`output`	Set when the channel is enabled, activated by software
	`dac_ddata_2`	`input[63:0]`	Data for channel 2, 4 samples
	`dac_valid_3`	`output`	DAC valid, used to read new data from the DMA
	`dac_enable_3`	`output`	Set when the channel is enabled, activated by software
	`dac_ddata_3`	`input[63:0]`	Data for channel 3, 4 samples
	`dac_dovf`	`input`	Data overflow input
	`dac_dunf`	`input`	Data underflow input

Detailed Architecture

Detailed Description

The top module, axi_ad9144, instantiates:

the JESD interface module
the core module
the AXI handling interface

The interface module, axi_ad9144_if, has at the input four samples for each of the four channels and arranges them in a format which is compatible with the Xilinx's JESD core.

The axi_ad9144_core module implements the channels modules and the DAC COMMON register map module. Each channel has it's own module, implementing PN7/PN15 data generation, inverse PN7/PN15, DDS data and fixed pattern generators. The module is configured through the DAC CHANNEL register map.

The up_axi module implements the AXI bus interface.

Register Map

Base (common to all cores)

Click to expand regmap

0x0000	0x0000	REG_VERSION				Version and Scratch Registers
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[31:0]	VERSION[31:0]	RO	0x00000000	Version number. Unique to all cores.
0x0001	0x0004	REG_ID				Version and Scratch Registers
		[31:0]	ID[31:0]	RO	0x00000000	Instance identifier number.
0x0002	0x0008	REG_SCRATCH				Version and Scratch Registers
		[31:0]	SCRATCH[31:0]	RW	0x00000000	Scratch register.
0x0003	0x000c	REG_CONFIG				Version and Scratch Registers
		[0]	IQCORRECTION_DISABLE	RO	0x0	If set, indicates that the IQ Correction module was not implemented. (as a result of a configuration of the IP instance)
		[1]	DCFILTER_DISABLE	RO	0x0	If set, indicates that the DC Filter module was not implemented. (as a result of a configuration of the IP instance)
		[2]	DATAFORMAT_DISABLE	RO	0x0	If set, indicates that the Data Format module was not implemented. (as a result of a configuration of the IP instance)
		[3]	USERPORTS_DISABLE	RO	0x0	If set, indicates that the logic related to the User Data Format (e.g. decimation) was not implemented. (as a result of a configuration of the IP instance)
		[4]	MODE_1R1T	RO	0x0	If set, indicates that the core was implemented in 1 channel mode. (e.g. refer to AD9361 data sheet)
		[5]	DELAY_CONTROL_DISABLE	RO	0x0	If set, indicates that the delay control is disabled for this IP. (as a result of a configuration of the IP instance)
		[6]	DDS_DISABLE	RO	0x0	If set, indicates that the DDS is disabled for this IP. (as a result of a configuration of the IP instance)
		[7]	CMOS_OR_LVDS_N	RO	0x0	CMOS or LVDS mode is used for the interface. (as a result of a configuration of the IP instance)
		[8]	PPS_RECEIVER_ENABLE	RO	0x0	If set, indicates the PPS receiver is enabled. (as a result of a configuration of the IP instance)
		[9]	SCALECORRECTION_ONLY	RO	0x0	If set, indicates that the IQ Correction module implements only scale correction. IQ correction must be enabled. (as a result of a configuration of the IP instance)
		[12]	EXT_SYNC	RO	0x0	If set the transport layer cores (ADC/DAC) have implemented the support for external synchronization signal.
		[13]	RD_RAW_DATA	RO	0x0	If set, the ADC has the capability to read raw data in register REG_CHAN_RAW_DATA from adc_channel.
0x0004	0x0010	REG_PPS_IRQ_MASK				PPS Interrupt mask
		[0]	PPS_IRQ_MASK	RW	0x1	Mask bit for the 1PPS receiver interrupt
0x0007	0x001c	REG_FPGA_INFO				FPGA device information Intel encoded values Xilinx encoded values
		[31:24]	FPGA_TECHNOLOGY	RO	0x0	Encoded value describing the technology/generation of the FPGA device (arria 10/7series)
		[23:16]	FPGA_FAMILY	RO	0x0	Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT or zynq, kintex, virtex)
		[15:8]	SPEED_GRADE	RO	0x0	Encoded value describing the FPGA's speed-grade
		[7:0]	DEV_PACKAGE	RO	0x0	Encoded value describing the device package. The package might affect high-speed interfaces
Tue Mar 14 10:17:59 2023

DAC Common (axi_ad)

Click to expand regmap

0x0010	0x0040	REG_RSTN				DAC Interface Control & Status
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[2]	CE_N	RW	0x0	Clock enable, default is enabled(0x0). An inverse version of the signal is exported out of the module to control clock enables
		[1]	MMCM_RSTN	RW	0x0	MMCM reset only (required for DRP access). Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
		[0]	RSTN	RW	0x0	Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
0x0011	0x0044	REG_CNTRL_1				DAC Interface Control & Status
		[0]	SYNC	RW	0x0	Setting this bit synchronizes channels within a DAC, and across multiple instances. This bit self clears.
		[1]	EXT_SYNC_ARM	RW	0x0	Setting this bit will arm the trigger mechanism sensitive to an external sync signal. Once the external sync signal goes high it synchronizes channels within a DAC, and across multiple instances. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.
		[2]	EXT_SYNC_DISARM	RW	0x0	Setting this bit will disarm the trigger mechanism sensitive to an external sync signal. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.
		[8]	MANUAL_SYNC_REQUEST	RW	0x0	Setting this bit will issue an external sync event if it is hooked up inside the fabric. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.
0x0012	0x0048	REG_CNTRL_2				DAC Interface Control & Status
		[16]	SDR_DDR_N	RW	0x0	Interface type (1 represents SDR, 0 represents DDR)
		[15]	SYMB_OP	RW	0x0	Select data symbol format mode (0x1)
		[14]	SYMB_8_16B	RW	0x0	Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b)
		[12:8]	NUM_LANES[4:0]	RW	0x0	Number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane)
		[7]	PAR_TYPE	RW	0x0	Select parity even (0x0) or odd (0x1).
		[6]	PAR_ENB	RW	0x0	Select parity (0x1) or frame (0x0) mode.
		[5]	R1_MODE	RW	0x0	Select number of RF channels 1 (0x1) or 2 (0x0).
		[4]	DATA_FORMAT	RW	0x0	Select data format 2's complement (0x0) or offset binary (0x1). NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
		[3:0]	RESERVED[3:0]	NA	0x00	Reserved
0x0013	0x004c	REG_RATECNTRL				DAC Interface Control & Status
		[7:0]	RATE[7:0]	RW	0x00	The effective dac rate (the maximum possible rate is dependent on the interface clock). The samples are generated at 1/RATE of the interface clock.
0x0014	0x0050	REG_FRAME				DAC Interface Control & Status
		[0]	FRAME	RW	0x0	The use of frame is device specific. Usually setting this bit to 1 generates a FRAME (1 DCI clock period) pulse on the interface. This bit self clears.
0x0015	0x0054	REG_STATUS1				DAC Interface Control & Status
		[31:0]	CLK_FREQ[31:0]	RO	0x00000000	Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock.
0x0016	0x0058	REG_STATUS2				DAC Interface Control & Status
		[31:0]	CLK_RATIO[31:0]	RO	0x00000000	Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
0x0017	0x005c	REG_STATUS3				DAC Interface Control & Status
		[0]	STATUS	RO	0x0	Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores.
0x0018	0x0060	REG_DAC_CLKSEL				DAC Interface Control & Status
		[0]	DAC_CLKSEL	RW	0x0	Allows changing of the clock polarity. Note: its default value is CLK_EDGE_SEL
0x001A	0x0068	REG_SYNC_STATUS				DAC Synchronization Status register
		[0]	DAC_SYNC_STATUS	RO	0x0	DAC synchronization status. Will be set to 1 while waiting for the external synchronization signal This bit has an effect only the EXT_SYNC synthesis parameter is set.
0x001C	0x0070	REG_DRP_CNTRL				DRP Control & Status
		[28]	DRP_RWN	RW	0x0	DRP read (0x1) or write (0x0) select (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
		[27:16]	DRP_ADDRESS[11:0]	RW	0x00	DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
		[15:0]	RESERVED[15:0]	RO	0x0000	Reserved for backwards compatibility
0x001D	0x0074	REG_DRP_STATUS				DAC Interface Control & Status
		[17]	DRP_LOCKED	RO	0x0	If set indicates the MMCM/PLL is locked
		[16]	DRP_STATUS	RO	0x0	If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
		[15:0]	RESERVED[15:0]	RO	0x0000	Reserved for backwards compatibility
0x001E	0x0078	REG_DRP_WDATA				DAC Interface Control & Status
		[15:0]	DRP_WDATA[15:0]	RW	0x0000	DRP write data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
0x001F	0x007c	REG_DRP_RDATA				DAC Interface Control & Status
		[15:0]	DRP_RDATA	RO	0x0000	DRP read data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
0x0020	0x0080	REG_DAC_CUSTOM_RD				DAC Read Configuration Data
		[31:0]	DAC_CUSTOM_RD[31:0]	RO	0x00000000	Custom Read of the available registers.
0x0021	0x0084	REG_DAC_CUSTOM_WR				DAC Write Configuration Data
		[31:0]	DAC_CUSTOM_WR[31:0]	RW	0x00000000	Custom Write of the available registers.
0x0022	0x0088	REG_UI_STATUS				User Interface Status
		[4]	IF_BUSY	RO	0x0	Interface busy. If set, indicates that the data interface is busy.
		[1]	UI_OVF	RW1C	0x0	User Interface overflow. If set, indicates an overflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.
		[0]	UI_UNF	RW1C	0x0	User Interface underflow. If set, indicates an underflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.
0x0023	0x008c	REG_DAC_CUSTOM_CTRL				DAC Control Configuration Data
		[31:0]	DAC_CUSTOM_CTRL[31:0]	RW	0x00000000	Custom Control of the available registers.
0x0028	0x00a0	REG_USR_CNTRL_1				DAC User Control & Status
		[7:0]	USR_CHANMAX[7:0]	RW	0x00	This indicates the maximum number of inputs for the channel data multiplexers. User may add different processing modules as inputs to the dac. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
0x002E	0x00b8	REG_DAC_GPIO_IN				DAC GPIO inputs
		[31:0]	DAC_GPIO_IN[31:0]	RO	0x00000000	This reads auxiliary GPI pins of the DAC core
0x002F	0x00bc	REG_DAC_GPIO_OUT				DAC GPIO outputs
		[31:0]	DAC_GPIO_OUT[31:0]	RW	0x00000000	This controls auxiliary GPO pins of the DAC core NOT-APPLICABLE if GPIO_DISABLE is set (0x1).
Tue Mar 14 10:17:59 2023

JESD TPL (up_tpl_common)

Click to expand regmap

0x00080	0x0200	REG_TPL_CNTRL				JESD, TPL Control
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[3:0]	PROFILE_SEL	RW	0x00	Selects one of the available deframer/framers from the transport layer. Valid only if `PROFILE_NUM` > 1.
0x00081	0x0204	REG_TPL_STATUS				JESD, TPL Status
		[3:0]	PROFILE_NUM	RO	0x00	Number of supported framer/deframer profiles.
0x00090	0x0240	REG_TPL_DESCRIPTOR_1				JESD, TPL descriptor for profile
		[31:24]	JESD_F	RO	0x00	Octets per Frame per Lane.
		[23:16]	JESD_S	RO	0x00	Samples per Converter per Frame.
		[15:8]	JESD_L	RO	0x00	Lane Count.
		[7:0]	JESD_M	RO	0x00	Converter Count.
0x00091	0x0244	REG_TPL_DESCRIPTOR_2				JESD, TPL descriptor for profile
		[7:0]	JESD_N	RO	0x00	Converter Resolution.
		[15:8]	JESD_NP	RO	0x00	Total Number of Bits per Sample.
0x00092	0x0248	REG_*				Profile 1, similar to registers 0x00010 to 0x00011.
0x00094	0x0250	REG_*				Profile 2, similar to registers 0x00010 to 0x00011.
Tue Mar 14 10:17:59 2023

DAC Channel (axi_ad*)

Click to expand regmap

0x0100	0x0400	REG_CHAN_CNTRL_1				DAC Channel Control & Status (channel - 0)
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[21:16]	DDS_PHASE_DW[5:0]	R	0x0000	The DDS phase data width offers the HDL parameter configuration with the same name. This information is used in conjunction with REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10. More info at https://wiki.analog.com/resources/fpga/docs/dds
		[15:0]	DDS_SCALE_1[15:0]	RW	0x0000	The DDS scale for tone 1. Sets the amplitude of the tone. The format is 1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on 16-bits, note that if you do use both channels and set both scale to 0x4000, it is over-range. The final output is (tone_1_fullscale * scale_1) (tone_2_fullscale * scale_2). NOT-APPLICABLE if DDS_DISABLE is set (0x1).
0x0101	0x0404	REG_CHAN_CNTRL_2				DAC Channel Control & Status (channel - 0)
		[31:16]	DDS_INIT_1[15:0]	RW	0x0000	The DDS phase initialization for tone 1. Sets the initial phase offset of the tone. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
		[15:0]	DDS_INCR_1[15:0]	RW	0x0000	Sets the frequency of the phase accumulator. Its value can be calculated by ; where f_out is the generated output frequency, and f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. If DDS_PHASE_DW is greater than 16(from REG_CHAN_CNTRL_1), the phase increment for tone 1 is extended in REG_CHAN_CNTRL_9. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
0x0102	0x0408	REG_CHAN_CNTRL_3				DAC Channel Control & Status (channel - 0)
		[15:0]	DDS_SCALE_2[15:0]	RW	0x0000	The DDS scale for tone 2. Sets the amplitude of the tone. The format is 1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on 16-bits, note that if you do use both channels and set both scale to 0x4000, it is over-range. The final output is (tone_1_fullscale * scale_1) + (tone_2_fullscale * scale_2). NOT-APPLICABLE if DDS_DISABLE is set (0x1).
0x0103	0x040c	REG_CHAN_CNTRL_4				DAC Channel Control & Status (channel - 0)
		[31:16]	DDS_INIT_2[15:0]	RW	0x0000	The DDS phase initialization for tone 2. Sets the initial phase offset of the tone. If DDS_PHASE_DW is greater than 16(from REG_CHAN_CNTRL_1), the phase init for tone 2 is extended in REG_CHAN_CNTRL_10. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
		[15:0]	DDS_INCR_2[15:0]	RW	0x0000	Sets the frequency of the phase accumulator. Its value can be calculated by ; where f_out is the generated output frequency, and f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. If DDS_PHASE_DW is greater than 16(from REG_CHAN_CNTRL_1), the phase increment for tone 2 is extended in REG_CHAN_CNTRL_10. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
0x0104	0x0410	REG_CHAN_CNTRL_5				DAC Channel Control & Status (channel - 0)
		[31:16]	DDS_PATT_2[15:0]	RW	0x0000	The DDS data pattern for this channel.
		[15:0]	DDS_PATT_1[15:0]	RW	0x0000	The DDS data pattern for this channel.
0x0105	0x0414	REG_CHAN_CNTRL_6				DAC Channel Control & Status (channel - 0)
		[2]	IQCOR_ENB	RW	0x0	if set, enables IQ correction. NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
		[1]	DAC_LB_OWR	RW	0x0	If set, forces DAC_DDS_SEL to 0x8, loopback If DAC_LB_OWR and DAC_PN_OWR are both set, they are ignored
		[0]	DAC_PN_OWR	RW	0x0	IF set, forces DAC_DDS_SEL to 0x09, device specific pnX If DAC_LB_OWR and DAC_PN_OWR are both set, they are ignored
0x0106	0x0418	REG_CHAN_CNTRL_7				DAC Channel Control & Status (channel - 0)
		[3:0]	DAC_DDS_SEL[3:0]	RW	0x00	Select internal data sources (available only if the DAC supports it). - 0x00: internal tone (DDS) - 0x01: pattern (SED) - 0x02: input data (DMA) - 0x03: 0x00 - 0x04: inverted pn7 - 0x05: inverted pn15 - 0x06: pn7 (standard O.150) - 0x07: pn15 (standard O.150) - 0x08: loopback data (ADC) - 0x09: pnX (Device specific e.g. ad9361) - 0x0A: Nibble ramp (Device specific e.g. adrv9001) - 0x0B: 16 bit ramp (Device specific e.g. adrv9001)
0x0107	0x041c	REG_CHAN_CNTRL_8				DAC Channel Control & Status (channel - 0)
		[31:16]	IQCOR_COEFF_1[15:0]	RW	0x0000	IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used, this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
		[15:0]	IQCOR_COEFF_2[15:0]	RW	0x0000	IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value and the format is 2's complement. If matrix multiplication is used, this is the channel Q coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
0x0108	0x0420	REG_USR_CNTRL_3				DAC Channel Control & Status (channel - 0)
		[25]	USR_DATATYPE_BE	RW	0x0	The user data type format- if set, indicates big endian (default is little endian). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		[24]	USR_DATATYPE_SIGNED	RW	0x0	The user data type format- if set, indicates signed (2's complement) data (default is unsigned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		[23:16]	USR_DATATYPE_SHIFT[7:0]	RW	0x00	The user data type format- the amount of right shift for actual samples within the total number of bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		[15:8]	USR_DATATYPE_TOTAL_BITS[7:0]	RW	0x00	The user data type format- number of total bits used for a sample. The total number of bits must be an integer multiple of 8 (byte aligned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		[7:0]	USR_DATATYPE_BITS[7:0]	RW	0x00	The user data type format- number of bits in a sample. This indicates the actual sample data bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
0x0109	0x0424	REG_USR_CNTRL_4				DAC Channel Control & Status (channel - 0)
		[31:16]	USR_INTERPOLATION_M[15:0]	RW	0x0000	This holds the user interpolation M value of the channel that is currently being selected on the multiplexer above. The total interpolation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		[15:0]	USR_INTERPOLATION_N[15:0]	RW	0x0000	This holds the user interpolation N value of the channel that is currently being selected on the multiplexer above. The total interpolation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
0x010A	0x0428	REG_USR_CNTRL_5				DAC Channel Control & Status (channel - 0)
		[0]	DAC_IQ_MODE[0]	RW	0x0	Enable complex mode. In this mode the driven data to the DAC must be a sequence of I and Q sample pairs.
		[1]	DAC_IQ_SWAP[1]	RW	0x0	Allows IQ swapping in complex mode. Only takes effect if complex mode is enabled.
0x010B	0x042c	REG_CHAN_CNTRL_9				DAC Channel Control & Status (channel - 0)
		[31:16]	DDS_INIT_1_EXTENDED[15:0]	RW	0x0000	The extended DDS phase initialization for tone 1. Sets the initial phase offset of the tone. The extended init(phase) value should be calculated according to DDS_PHASE_DW value from REG_CHAN_CNTRL_1 NOT-APPLICABLE if DDS_DISABLE is set (0x1).
		[15:0]	DDS_INCR_1_EXTENDED[15:0]	RW	0x0000	Sets the frequency of tone 1's phase accumulator. Its value can be calculated by ; Where f_out is the generated output frequency, DDS_PHASE_DW value can be found in REG_CHAN_CNTRL_1 in case DDS_PHASE_DW is not 16, f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
0x010C	0x0430	REG_CHAN_CNTRL_10				DAC Channel Control & Status (channel - 0)
		[31:16]	DDS_INIT_2_EXTENDED[15:0]	RW	0x0000	The extended DDS phase initialization for tone 2. Sets the initial phase offset of the tone. The extended init(phase) value should be calculated according to DDS_PHASE_DW value from REG_CHAN_CNTRL_2 NOT-APPLICABLE if DDS_DISABLE is set (0x1).
		[15:0]	DDS_INCR_2_EXTENDED[15:0]	RW	0x0000	Sets the frequency of tone 2's phase accumulator. Its value can be calculated by ; Where f_out is the generated output frequency, DDS_PHASE_DW value can be found in REG_CHAN_CNTRL_2 in case DDS_PHASE_DW is not 16, f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
0x0110	0x0440	REG_*				Channel 1, similar to registers 0x100 to 0x10f.
0x0120	0x0480	REG_*				Channel 2, similar to registers 0x100 to 0x10f.
0x01F0	0x07c0	REG_*				Channel 15, similar to registers 0x100 to 0x10f.
Fri Sep 8 16:01:53 2023

Software Guidelines

The software for this IP can be found as part of the DAQ2 Reference Design at: No-OS Software
Linux is supported also using ADI Linux repository

References

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Wiki

Analog Devices Wiki

Table of Contents

AXI_AD9144 (Obsolete)

Features

Block Diagram

Configuration Parameters

Interface

Detailed Architecture

Detailed Description

Register Map

Base (common to all cores)

DAC Common (axi_ad)

JESD TPL (up_tpl_common)

DAC Channel (axi_ad*)

Software Guidelines

References

Analog Devices Wiki

Table of Contents

AXI_AD9144 (Obsolete)

Features

Block Diagram

Configuration Parameters

Interface

Detailed Architecture

Detailed Description

Register Map

Base (common to all cores)

DAC Common (axi_ad)

JESD TPL (up_tpl_common)

DAC Channel (axi_ad*)

Software Guidelines

References

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