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AXI_AD9144 IP core

The axi_ad9144 IP core can be used to interface the AD9144 DAC. An AXI Memory Map interface is used for configuration. Data is sent in a format that can be transmitted by Xilinx's JESD IP.

More about the generic framework interfacing DACs can be read here: axi_dac_ip.

Features

  • AXI based configuration
  • Hardware PRBS generation
  • Hardware DDS generation
  • Xilinx Vivado compatible
  • Altera Quartus compatible

Block Diagram

 AXI_AD9144 Block diagram

Configuration Parameters

Name Description Default Value
ID Core ID should be unique for each AD9144 IP in the system 0
QUAD_OR_DUAL_N Selects if 4 lanes (1) or 2 lanes (0) are connected 1
DAC_DATAPATH_DISABLE If set, the DDS modules are not implemented 0

Interface

Interface Pin Type Description
jesd interface Data to be connected to the JESD core
tx_clk* input Line rate / 40
tx_ready* input Not used in the IP, just for interface compatibility reasons
tx_data output[255/127:0] Data to be sent to the JESD core. 256 bit wide for QUAD operation, and 128 bit for DUAL operation
tx_valid* output Always set to 1, for interface compatibility reasons
s axi AXI Slave Memory Map interface
dma interface FIFO interface for connecting to the DMA
dac_clk output Loopback of the tx_clk. Most of the modules of the core run on this clock
dac_valid_0 output DAC valid, used to read new data from the DMA
dac_enable_0 output Set when the channel is enabled, activated by software
dac_ddata_0 input[63:0] Data for channel 0, 4 samples
dac_valid_1 output DAC valid, used to read new data from the DMA
dac_enable_1 output Set when the channel is enabled, activated by software
dac_ddata_1 input[63:0] Data for channel 1, 4 samples
dac_valid_2 output DAC valid, used to read new data from the DMA
dac_enable_2 output Set when the channel is enabled, activated by software
dac_ddata_2 input[63:0] Data for channel 2, 4 samples
dac_valid_3 output DAC valid, used to read new data from the DMA
dac_enable_3 output Set when the channel is enabled, activated by software
dac_ddata_3 input[63:0] Data for channel 3, 4 samples
dac_dovf input Data overflow input
dac_dunf input Data underflow input

Detailed Architecture

 AXI_AD9144 IP architecture?800x600

Detailed Description

The top module, axi_ad9144, instantiates:

  • the JESD interface module
  • the core module
  • the AXI handling interface


The interface module, axi_ad9144_if, has at the input four samples for each of the four channels and arranges them in a format which is compatible with the Xilinx's JESD core.

The axi_ad9144_core module implements the channels modules and the DAC COMMON register map module. Each channel has it's own module, implementing PN7/PN15 data generation, inverse PN7/PN15, DDS data and fixed pattern generators. The module is configured through the DAC CHANNEL register map.

The up_axi module implements the AXI bus interface.

Register Map

Base (common to all cores)

Click to expand regmap

DAC Common (axi_ad)

Click to expand regmap

JESD TPL (up_tpl_common)

Click to expand regmap

DAC Channel (axi_ad*)

Click to expand regmap

Software Guidelines

The software for this IP can be found as part of the DAQ2 Reference Design at: No-OS Software
Linux is supported also using ADI Linux repository

References

resources/fpga/docs/axi_ad9144.1634109458.txt.gz · Last modified: 13 Oct 2021 09:17 by Iulia Moldovan