This version is outdated by a newer approved version.
This version (06 Jan 2021 16:14) was approved by Robin Getz.The Previously approved version (21 Oct 2019 17:57) is available.
This version (06 Jan 2021 16:14) was approved by Robin Getz.The Previously approved version (21 Oct 2019 17:57) is available.This is an old revision of the document!
Table of Contents
ADRV936x RF SOM Hardware
Whether you want to understand the changes between revisions, or just understand how to probe the PCB, this is where all the information should be.
ADRV936x - Mechanical
The ADRV9361-Z7035 SDR 2×2 SOM uses a 20 layer PCB that measures 2.440” x 3.937” (62 mm x 100 mm). The 62mm x 100mm form factor is compatible with the DP10062 “Sick of Beige v1.0” specification from dangerousprototypes.com.
Connectors
The MicroHeaders used on ADRV9361-Z7035 are FCI 0.8mm BergStak®100-position Dual Row, BTB Vertical Receptacles (61082-101400LF). These receptacles mate with any of the FCI 0.8mm BergStak® 100-position Dual Row BTB Vertical Plugs (61083-10x400LF) to provide variable stack heights of 5mm, 6mm, 7mm or 8mm. The SOM uses the FCI “receptacle” while carrier cards use the “plug”. Both receptacle and plug include a PCB locator peg that can be used to design precisely mated SOM and carrier layouts.
More information about these connectors can be found here .
Dimensions
The physical dimensions of the connectors, mounting holes and PCB is common between the ADRV9361-Z7035 and the ADRV9364-Z7020.
The Footprint is common between the two parts:
- Carrier Card Connector Dimensions:
Pinout
The connector pinouts are a superset:
ADRV9361-Z7035 Hardware
Revision F (WIP)
Still under review.
Revision E
This is the current shipping version.
- Rev E Allegro Board File (This file is compressed). Get the Allegro FREE Physical Viewer (You need 16.6 or higher).
Why do a Rev F?
- The schematic did not change. We only made an adjustment to the layout.
- The RF traces were modified to improve the insertion loss and the return loss as well as the EVM.
- Rev E has high attenuation on TX above 4.5 GHz
Revision C (First publicly available revision)
This is the first publicly available revision.
Why do a Rev D?
- Improved the power structure and increased the 0.95V current from 2A to 6A
- Added a 1000BASE-KX option for the Ethernet Phy (Ethernet Operation over Electrical Backplanes)
- Improved the layout to accommodate the power changes.
ADRV9364-Z7020 Hardware
Revision D
This is the current shipping version.
-
- There was a small typo in the rev D0 of the schematics (below), the net named
*_EN_AGC, was tied to theENABLEpin, and the net called*_ENABLEwas tied to theEN_AGCpin. This is fixed/updated in this schematic. copper/layout does not change, only the designation on the wire (for clarity).
-
- This has the notation error described above.
- Rev D Allegro Board File (This file is compressed). Get the Allegro FREE Physical Viewer (You need 16.6 or higher).
Revision C
This is the first publicly available revision.
Why do a Rev D?
- Improved the power structure and increased the 1V current from 2A to 4A
- Improved the layout to accommodate the power changes.
- Added a 1000BASE-KX option for the Ethernet Phy (Ethernet Operation over Electrical Backplanes)
- Improved the RF traces to have better insertion loss and return loss.
Carrier Support
The ADRV9361-Z7035 supports all features on the ADRV1CRR-FMC carrier board. The ADRV9364-Z7020 supports a subset of features because the Zynq Z7020 has fewer available user I/Os. For the ADRV9364-Z7020 it is recommended to use the ADRV1CRR-BOB carrier.
Support
Please refer to EngineerZone with questions on hardware/schematics/or using the ADRV936x RF SOMs.
resources/eval/user-guides/adrv936x_rfsom/hardware.1582554719.txt.gz · Last modified: 24 Feb 2020 15:31 by Adrian Costina