This version (17 Nov 2022 15:24) was approved by Liviu-Mihai Iacob, Istvan Szekely.The Previously approved version (26 Mar 2021 18:07) is available.
Table of Contents
AD9083 FMC Card HDL Reference Design
Overview
The AD9083 is a 16-bit, 16 channel with 125 MHz bandwidth per channel (2 GSPS total) analog-to-digital converter (ADC) featuring an on-chip programmable, single-pole antialiasing filter and termination resistor that is designed for low power, small size, and ease of use.
The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges.
The AD9083-FMC reference design is a processor based (e.g. Microblaze) embedded system. The design consists of a receive chain.
The receive chain transports the captured samples from ADC to the system memory (DDR). Before transferring the data to DDR the samples are stored in a 33Mbit buffer implemented on block rams from the FPGA fabric (util_adc_fifo) or 65k samples per channel.
All cores from the receive chain are programmable through an AXI-Lite interface.
Supported Devices
Supported Carriers
Required Hardware
Block Diagram
For both platforms, the link is set for full bandwidth mode and operate with the following parameters:
Deframer paramaters: L=4, M=16, F=8, S=1, N’=16
GTREFCLK – 500MHz
LINKCLK(Lane Rate/40) – 250MHz
DEVICECLK - 125 MHz
ADCCLK – 2000MHz
JESD204B Lane Rate – 10Gbps
Beacause of the F=8 parameter the JESD Link IP will have different input and output frequencies and bus widths. Data will enter the IP on 4 32bit wide channels (128b) at 250MHz (link clock) and will exit on a 256bit interface clocked at 125MHz (device clock). The transport layer component presents on its output 256 bits at once on every clock cycle, representing 1 sample per converter. The receive chain is then transferred to the DDR using a DMA.
The data path and clock domains are depicted on the below diagram:
Xilinx
The design has one JESD receive chain with 4 lanes at rate of 10Gbps. The JESD receive chain consists of a physical layer represented by an XCVR module, a link layer represented by an RX JESD LINK module and transport layer represented by a RX JESD TPL module. The links operate in Subclass 0 since it is not using the SYSREF signal.
Intel
The design has one JESD receive chain with 4 lanes at rate of 10Gbps. The JESD receive chain consists of a physical and link layer represented by AD9083_JESD204 module, and transport layer represented by a AXI_AD9083 module. The links operate in Subclass 0 since it is not using the SYSREF signal.
Building the HDL project
ADI does not distribute the bit/elf files of these projects so they must be built from the sources available here. To get the source you must clone the HDL repository. Then go to the /projects/ad9083_fmc/zcu102 location and run the make command by typing in your command prompt:
Linux/Cygwin
user@analog:~$ cd hdl/projects/ad9083_fmc/zcu102 user@analog:~/hdl/projects/ad9083_fmc/zcu102$ make
A more comprehensive build guide can be found in the HDL User Guide.
HDL Downloads
Software sources
More Information
Support
Analog Devices will provide limited online support for anyone using the reference design with Analog Devices components via the EngineerZone.
resources/eval/user-guides/ad9083/ad9083_evb_reference_hdl.txt · Last modified: 17 Nov 2022 15:24 by Liviu-Mihai Iacob