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resources:fpga:xilinx:interposer:ad9789 [19 Jun 2012 21:53] – updated rejeesh kuttyresources:fpga:xilinx:interposer:ad9789 [28 Jan 2021 19:14] (current) – update arrow links after their web site update Robin Getz
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 The [[adi>AD9789]] is a flexible four channel QAM encoder, interpolator and upconverter combined with a high performance, 2.4GSPS, 14-bit, RF digital-to-analog converter (DAC). This reference design includes DDS generators that drives all channels of the device. The programming is done via the USB-SPI interface. The [[adi>AD9789]] is a flexible four channel QAM encoder, interpolator and upconverter combined with a high performance, 2.4GSPS, 14-bit, RF digital-to-analog converter (DAC). This reference design includes DDS generators that drives all channels of the device. The programming is done via the USB-SPI interface.
  
-**HW Platform(s):** [[http://www.xilinx.com/ml605|Virtex-6 ML605 (Xilinx)]] and [[http://www.analog.com/en/content/eb_ad9789_evaluation_board/fca.html|AD9789 Evaluation Board (ADI)]], [[http://www.analog.com/en/digital-to-analog-converters/da-converters/ad-dac-fmc/products/product.html|DAC FMC Interposer Board (ADI)]] \\ +===== Supported Devices ===== 
-**System:** Microblaze, AXI, UART+ 
 +  * [[adi>en/digital-to-analog-converters/high-speed-da-converters/ad9789/products/EVAL-AD9789/eb.html|AD9789 Evaluation Board]] 
 +  * [[adi>AD-DAC-FMC|DAC FMC Interposer Board]] 
 + 
 +===== Supported Carriers ===== 
 + 
 +  * [[xilinx>ML605]]  
 + 
  
 ===== Quick Start Guide ===== ===== Quick Start Guide =====
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   * Xilinx ISE 14.1 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).   * Xilinx ISE 14.1 (Programmer (IMPACT) is sufficient for the demo and is available on Webpack).
   * A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.   * A UART terminal (Tera Term/Hyperterminal), Baud rate 57600.
-  * ADI DPG DAC Software Suite [[http://www.analog.com/en/digital-to-analog-converters/da-converters/products/evaluation-boardstools/CU_eb_DPG_high_speed_DAC_eval_platform/resources/fca.html|(available here)]].+  * ADI DPG DAC Software Suite [[adi>en/digital-to-analog-converters/da-converters/products/evaluation-boardstools/CU_eb_DPG_high_speed_DAC_eval_platform/resources/fca.html|(available here)]].
  
 ==== Bit file ==== ==== Bit file ====
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 ==== QAM Mapper Mode ==== ==== QAM Mapper Mode ====
  
-The interface is minimally tested. The functionality is not tested! 
  
 ==== SRRC Filter Mode ==== ==== SRRC Filter Mode ====
  
-The interface is minimally tested. The functionality is not tested! 
  
 ==== Interpolation Filter Mode ==== ==== Interpolation Filter Mode ====
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   * Click on "Run Continously" button.   * Click on "Run Continously" button.
-  * Interface Control: Set DCO_INV to On position.+  * Interface Control: Set DCO_INV to OFF position (change it to ON if the spectrum has unwanted spurs).
   * Interface Control: Set I/F_MODE to Channelizer mode.   * Interface Control: Set I/F_MODE to Channelizer mode.
   * Interface Control: Set CHANPRI to ON position (enabled).   * Interface Control: Set CHANPRI to ON position (enabled).
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   * Click on "Run Continously" button.   * Click on "Run Continously" button.
-  * Interface Control: Set DCO_INV to On position.+  * Interface Control: Set DCO_INV to OFF position (change it to ON if the spectrum has unwanted spurs).
   * Interface Control: Set I/F_MODE to QDUC mode.   * Interface Control: Set I/F_MODE to QDUC mode.
   * Interface Control: Set CHANPRI to ON position (enabled).   * Interface Control: Set CHANPRI to ON position (enabled).
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 ===== Downloads ===== ===== Downloads =====
  
-{{:resources:fpga:xilinx:interposer:cf_ad9789_ebz.tar.gz|ML605 Reference Design Source Code}}\\+FPGA Referece Designs: 
 +<WRAP round download 80%> 
 +  * **ML605 (source files) ** {{:resources:fpga:xilinx:interposer:cf_ad9789_ebz_edk_14_4_2013_03_25.tar.gz}} 
 +  * **ML605 (bit/sw files) ** {{:resources:fpga:xilinx:interposer:cf_ad9789_ebz_sw_14_4_2013_03_25.tar.gz}} 
 +</WRAP>
  
 +Only Xilinx coregen xco files are provided with the reference design. You must regenerate the IP core files using this file. See [[/resources/eval/user-guides/ad-fmcomms1-ebz/reference_hdl|generating Xilinx netlist/verilog files from xco files]] for details.
  
-===== Notes =====+<WRAP round help 80%> 
 +  * Questions? [[ez>fpga|Ask Help & Support]]. 
 +</WRAP>
  
-The following two files are removed from the tar file. 
  
-  * pcores/axi_ad9789_v1_00_a/netlist/cf_ddsx_1.ngc 
-  * pcores/axi_ad9789_v1_00_a/hdl/verilog/cf_ddsx_1.v 
  
-To use the reference design as it is, re-generate the Xilinx DDS core for a single sine output (16bit) in full range mode. 
  
 ===== Tar file contents ===== ===== Tar file contents =====
  
-The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[http://www.xilinx.com/support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.+The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to [[xilinx>support/documentation/dt_edk_edk13-2.htm|Xilinx EDK documentation]] for details.
  
 | license.txt | ADI license & copyright information. | | license.txt | ADI license & copyright information. |
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 ===== More information ===== ===== More information =====
  
-  * [[http://www.vita.com/fmc.html|VITA's FMC info]]+  * [[http://www.vita.com/fmc|VITA's FMC info]]
   * [[ez>community/fpga|Ask questions about the FPGA reference design]]   * [[ez>community/fpga|Ask questions about the FPGA reference design]]
  
  
  
resources/fpga/xilinx/interposer/ad9789.1340135592.txt.gz · Last modified: 19 Jun 2012 21:53 (external edit)

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