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The AD9789 is a flexible four channel QAM encoder, interpolator and upconverter combined with a high performance, 2.4GSPS, 14-bit, RF digital-to-analog converter (DAC). This reference design includes DDS generators that drives all channels of the device. The programming is done via the USB-SPI interface.
HW Platform(s): Virtex-6 ML605 (Xilinx) and AD9789 Evaluation Board (ADI), DAC FMC Interposer Board (ADI)
System: Microblaze, AXI, UART
The bit file provided combines the FPGA bit file and the SDK elf files. It may be used for a quick check on the system. All you need is the hardware and a PC running a UART terminal, ADI DAC software and the programmer (IMPACT).
To begin make the following connections (see image below):
Setup the clock source to be 2.4GHz/6dBm. After the hardware setup, turn the power on to the ML605 and the AD9789-EBZ boards.
The reference design primarily supports four modes of operation.
Mode | Key-Select | Bus-Width | Data-Width | Data-Format | First Block Enabled | Description |
0x0 | 'a' | 32 | 8 | Real | QAM mapper | Channelizer Mode. |
0x1 | 'b' | 32 | 8 | Complex | SRRC filter | Channelizer Mode. |
0x2 | 'c' | 32 | 16 | Complex | Interpolation Filter | Channelizer Mode. |
0x3 | 'd' | 32 | 16 | Complex | N/A | QDUC Mode. |
The reference design is NOT fully verified across all the modes. The delay/latency parameters may have to be adjusted depending on various features selected.
The interface is minimally tested. The functionality is not tested!
The interface is minimally tested. The functionality is not tested!
Start ADI- AD9789 SPI program (see screenshot below)-
If programming was successful, you should be seeing messages appear on the terminal as shown in figure below.
Select 'c' for the interpolation filter mode. The spectrum should appear as shown below. The DDS is set to 500KHz to 2000KHz.
Start ADI- AD9789 SPI program (see screenshot below)-
If programming was successful, you should be seeing messages appear on the terminal as shown in figure below.
Select 'd' for the qduc mode. The spectrum should appear as shown below. The DDS is set to 3MHz.
The reference design consists of a DDS module and a lvds interface. The DDS module consists of a Xilinx DDS core and DDR based DDS. It is possible to change the output data delay with respect to the DCO clock, as well as the FS to data delay. See the regmap file and the SDK c file.
Refer to the regmap.txt file inside the pcore.
The following two files are removed from the tar file.
To use the reference design as it is, re-generate the Xilinx DDS core for a single sine output (16bit) in full range mode.
The tar file contains, in most cases, the following files and/or directories. To rebuild the reference design simply double click the XMP file and run the tool. To build SDK, select a workspace and use the C file to build the elf file. Please refer to Xilinx EDK documentation for details.
license.txt | ADI license & copyright information. |
system.mhs | MHS file. |
system.xmp | XMP file (use this file to build the reference design). |
data/ | UCF file and/or DDR MIG project files. |
docs/ | Documentation files (Please note that this wiki page is the documentation for the reference design). |
sw/ | Software (Xilinx SDK) & bit file(s). |
cf_lib/edk/pcores | The pcores directory. |