| Both sides previous revisionPrevious revisionNext revision | Previous revision |
| resources:fpga:peripherals:spi_engine:offload [27 May 2015 14:19] – [Configuration Parameters] Lars-Peter Clausen | resources:fpga:peripherals:spi_engine:offload [19 Apr 2023 21:47] (current) – [Signal and Interface Pins] Jorge Marques |
|---|
| |
| ^ Name ^ Description ^ | ^ Name ^ Description ^ |
| | [[github>hdl?dev/library/spi_engine/spi_engine_offload/spi_engine_offload.v|spi_engine_offload.v]] | Verilog source for the peripheral. | | | [[github>hdl?master/library/spi_engine/spi_engine_offload/spi_engine_offload.v|spi_engine_offload.v]] | Verilog source for the peripheral. | |
| | [[github>hdl?dev/library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl|spi_engine_offload_ip.tcl]] | TCL script to generate the Vivado IP-integrator project for the peripheral. | | | [[github>hdl?master/library/spi_engine/spi_engine_offload/spi_engine_offload_ip.tcl|spi_engine_offload_ip.tcl]] | TCL script to generate the Vivado IP-integrator project for the peripheral. | |
| |
| ===== Configuration Parameters ===== | ===== Configuration Parameters ===== |
| |
| ^ Name ^ Description ^ Default ^ | ^ Name ^ Description ^ Default ^ |
| | ''SPI_CLK_ASYNC'' | If set to 1 the ctrl_clk and spi_clk are assumed to be asynchronous | 0 | | | ''SPI_CLK_ASYNC'' | If set to 1 the ''ctrl_clk'' and ''spi_clk'' are assumed to be asynchronous | 0 | |
| | ''CMD_MEM_ADDR_WIDTH'' | Configures the size of the command stream storage. The size is ''2<nowiki>**</nowiki>CMD_MEM_ADDR_WIDTH'' entries. | 4 | | | ''CMD_MEM_ADDR_WIDTH'' | Configures the size of the command stream storage. The size is ''2<nowiki>**</nowiki>CMD_MEM_ADDR_WIDTH'' entries. | 4 | |
| | ''SDO_MEM_ADDR_WIDTH'' | Configures the size of the SDO data stream storage. The size is ''2<nowiki>**</nowiki>SDO_MEM_ADDR_WIDTH'' entries. | 4 | | | ''SDO_MEM_ADDR_WIDTH'' | Configures the size of the SDO data stream storage. The size is ''2<nowiki>**</nowiki>SDO_MEM_ADDR_WIDTH'' entries. | 4 | |
| ^ Name ^ Type ^ Description ^ | ^ Name ^ Type ^ Description ^ |
| | ''ctrl_clk'' | Clock | The ''spi_engine_offload_ctrl'' signals are synchronous to this clock. | | | ''ctrl_clk'' | Clock | The ''spi_engine_offload_ctrl'' signals are synchronous to this clock. | |
| | ''spi_clk'' | Clock | The ''spi_engine_ctrl'' siganls, ''offload_sdi'' signals and trigger are synchronous to this clock. | | | ''spi_clk'' | Clock | The ''spi_engine_ctrl'' signals, ''offload_sdi'' signals and trigger are synchronous to this clock. | |
| | ''spi_resetn'' | Synchronous active low reset | Resets the internal state machine of the core. | | | ''spi_resetn'' | Synchronous active low reset | Resets the internal state machine of the core. | |
| | ''trigger'' | Input | When asserted the stored command and data stream is send out on the ''spi_engine_ctrl'' interface. | | | ''trigger'' | Input | When asserted the stored command and data stream is send out on the ''spi_engine_ctrl'' interface. | |
