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resources:fpga:peripherals:spi_engine:engine [30 Mar 2015 11:46] – Lars-Peter Clausen | resources:fpga:peripherals:spi_engine:engine [04 Sep 2019 12:44] (current) – Fix source links and some grammar mistakes Istvan Csomortani |
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{{ :resources:fpga:peripherals:spi_engine:spi_engine_execution.png|}} | {{ :resources:fpga:peripherals:spi_engine:spi_engine_execution.png|}} |
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The SPI Engine Execution peripheral forms the heart of the SPI Engine framework. It is responsible for handling a SPI Engine control stream and translate it into low-level SPI bus transactions. | The SPI Engine Execution peripheral forms the heart of the SPI Engine framework. It is responsible for handling a SPI Engine control stream and translates it into low-level SPI bus transactions. |
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===== Files ===== | ===== Files ===== |
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^ Name ^ Description ^ | ^ Name ^ Description ^ |
| .v | Verilog source for the peripheral. | | | [[github>hdl?master/library/spi_engine/spi_engine_execution/spi_engine_execution.v|spi_engine_execution.v]] | Verilog source for the peripheral. | |
| .tcl | TCL script to generate the Vivado IP-integrator project for the peripheral. | | | [[github>hdl?master/library/spi_engine/spi_engine_execution/spi_engine_execution_ip.tcl|spi_engine_execution_ip.tcl]] | TCL script to generate the Vivado IP-integrator project for the peripheral. | |
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===== Configuration Parameters ===== | ===== Configuration Parameters ===== |
^ Name ^ Description ^ Default ^ | ^ Name ^ Description ^ Default ^ |
| ''NUM_CS'' | Number of chip-select signals for the SPI bus (min: 1, max: 8) | 1 | | | ''NUM_CS'' | Number of chip-select signals for the SPI bus (min: 1, max: 8) | 1 | |
| | ''DEFAULT_SPI_CFG'' | Reset configuration value for the [[.:instruction_format#spi_configuration_register|SPI configuration register]] | 0 | |
| | ''DEFAULT_CLK_DIV'' | Reset configuration value for the [[.:instruction_format#prescaler_configuration_register|prescaler clock divider register]] | 0 | |
| | ''DATA_WIDTH'' | Data width of the parallel data stream. Will define the transaction's granularity. Supported values: 8/16/24/32| 8 | |
| | ''NUM_OF_SDI'' | Number of multiple SDI lines, (min: 1, max: 8) | 1 | |
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===== Signal and Interface Pins ===== | ===== Signal and Interface Pins ===== |
^ Name ^ Type ^ Description ^ | ^ Name ^ Type ^ Description ^ |
| ''clk'' | Clock | All other signals are synchronous to this clock. | | | ''clk'' | Clock | All other signals are synchronous to this clock. | |
| ''resetn'' | Synchronous active low reset | Resets the internal state machine of the core. | | | ''resetn'' | Synchronous active-low reset | Resets the internal state machine of the core. | |
| ''active'' | Output | Indicates whether the peripheral is currently active and processing commands. | | | ''active'' | Output | Indicates whether the peripheral is currently active and processing commands. | |
| ''ctrl'' | [[SPI Engine Control Interface]] slave | SPI Engine Control stream that contains commands and data for the execution module. | | | ''ctrl'' | [[SPI Engine Control Interface]] slave | SPI Engine Control stream that contains commands and data for the execution module. | |
===== Theory of Operation ===== | ===== Theory of Operation ===== |
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The ''active'' signal is be asserted as long as the peripheral is busy executing incoming commands. | The SPI Engine Execution module implements the physical access to the SPI bus. It implements a small but powerful programmable state machine that translates a SPI Engine command stream into low-level SPI bus access. |
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{{:resources:fpga:peripherals:spi_engine:spi_engine.svg|}} | Communication with a command stream generator happens via the ''ctrl'' interface and the low-level SPI access is handled on the ''spi'' interface. The ''active'' signal is asserted as long as the peripheral is busy executing incoming commands. |
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| Internally the SPI Engine execution module consists of an instruction encoder that translates the incoming commands into an internal control signal, a multi-function counter and compares unit that is responsible for handling the timing and a shift register which holds the received and transmitted SPI data. |
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| The module has an optional programmable pre-scaler register that can be used to divide the external clock to the counter and compare unit. |
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| {{:resources:fpga:peripherals:spi_engine:spi_engine.svg|}} |
===== More Information ===== | ===== More Information ===== |
* [[.|SPI Engine Framework]] | * [[.|SPI Engine Framework]] |