This version is outdated by a newer approved version.
This version (30 Mar 2015 11:46) is a draft.
Approvals: 0/1
This version (30 Mar 2015 11:46) is a draft.Approvals: 0/1
This is an old revision of the document!
Table of Contents
SPI Engine Execution FPGA Peripheral
The SPI Engine Execution peripheral forms the heart of the SPI Engine framework. It is responsible for handling a SPI Engine control stream and translate it into low-level SPI bus transactions.
Files
| Name | Description |
|---|---|
| .v | Verilog source for the peripheral. |
| .tcl | TCL script to generate the Vivado IP-integrator project for the peripheral. |
Configuration Parameters
| Name | Description | Default |
|---|---|---|
NUM_CS | Number of chip-select signals for the SPI bus (min: 1, max: 8) | 1 |
Signal and Interface Pins
| Name | Type | Description |
|---|---|---|
clk | Clock | All other signals are synchronous to this clock. |
resetn | Synchronous active low reset | Resets the internal state machine of the core. |
active | Output | Indicates whether the peripheral is currently active and processing commands. |
ctrl | SPI Engine Control Interface slave | SPI Engine Control stream that contains commands and data for the execution module. |
spi | SPI bus interface master | Low-level SPI bus interface that is controlled by peripheral. |
Theory of Operation
The active signal is be asserted as long as the peripheral is busy executing incoming commands.
More Information
resources/fpga/peripherals/spi_engine/engine.1427708788.txt.gz · Last modified: 30 Mar 2015 11:46 by Lars-Peter Clausen