This version (21 Jul 2022 12:42) was approved by Alin-Tudor Sferle.The Previously approved version (12 Apr 2022 13:19) is available.
Table of Contents
UTIL_MII_TO_RMII
The util_mii_to_rmii IP core is designed to interface the Zynq-7000/Zynq UltraScale+ MPSoC - PS Gigabit Ethernet MAC and Reduced Media Independent Interface (RMII) ADIN1300 PHY from the CN0506 Dual PHY Ethernet evaluation board.
Features
- configurable interface for the MAC block (Media Independent Interface - MII or Gigabit Media Independent Interface - GMII)
- configurable data rate for the MAC block and PHY chip
Files
| Name | Description |
|---|---|
| mac_phy_link.v | Verilog source for the conversion between MII MAC block interface and RMII PHY chip interface. |
| phy_mac_link.v | Verilog source for the conversion between RMII PHY chip interface and MII MAC block interface. |
| util_mii_to_rmii.v | Verilog source for the main module made of the MII and RMII interfaces. |
Block Diagram
Configuration Parameters
| Name | Description | Default |
|---|---|---|
INTF_CFG | MAC Block Interface Selection (0 = GMII, 1 = MII). | 0 |
RATE_10_100 | Data Rate Selection (0 = 100 Mbps, 1 = 10 Mbps). | 0 |
Interfaces
| Interface | Pin | Type | Description |
|---|---|---|---|
MAC-PHY Link (MII MAC Block to RMII PHY) | MII to RMII conversion signals | ||
mac_txd | input [3:0] | MII Transmit Data | |
mac_tx_en | input | MII Transmit Enable | |
mac_tx_er | input | MII Transmit Error | |
mii_tx_clk | output | MII Transmit Clock | |
rmii_txd | output [1:0] | RMII (PHY) Transmit Data | |
rmii_tx_en | output | RMII (PHY) Transmit Enable | |
PHY-MAC Link (RMII PHY to MII MAC Block) | RMII to MII conversion signals | ||
mii_col | output | MII Collision Detect signal (only in half-duplex mode) | |
mii_crs | output | MII Carrier Sense signal (only in half-duplex mode) | |
mii_rxd | input [3:0] | MII Receive Data | |
mii_rx_clk | input | MII Receive Clock | |
mii_rx_dv | input | MII Receive Data Valid | |
mii_rx_er | input | MII Receive Error | |
phy_crs_dv | output | PHY (RMII) Carrier Sense/Data Valid | |
phy_rxd | output[1:0] | PHY (RMII) Receive Data | |
phy_rx_er | output | PHY (RMII) Receive Error | |
External | |||
ref_clk | input | Reference Clock for MII to RMII IP core | |
reset_n | input | Active-Low reset for MII to RMII IP core | |
Register Map
There is no register map defined for this IP core.
Theory of operation
The following timing diagrams illustrate different signal protocols for MII and RMII interfaces at data rates of 100 and 10 Mbps.
Receive Transactions
- RMII (PHY) receive transaction at 100 Mbps with no errors and phy_crs_dv asserted until the final packet dibit. According to the RMII Specification Rev. 1.2, after the assertion of phy_crs_dv, several 00's dibits can precede the preamble 01's dibits. The preamble is composed of 28 “01” dibits and the start of frame delimiter of 3 “01” dibits and one “11” dibit followed by the frame containing 64-1522 bytes:
- RMII (PHY) receive transaction at 100 Mbps with no errors and phy_crs_dv toggling at 25 MHz starting on a nibble boundary and indicates the PHY has lost the carrier but has accumulated nibbles to transfer:
- At a data rate of 10 Mbps (ref_clk frequency divided by 10), mii_rxd will be sampled every
cycle.
- MII receive transaction converted from RMII (PHY) receive transaction at 100 Mbps. In the MII mode mii_rx_dv and mii_rxd will be sampled on the falling edge of the 25 MHz mii_rx_clk and when mii_rx_dv is de-asserted, mii_rxd will present 0b0000 to the Ethernet MAC:
Transmit Transactions
- MII transmit transaction at 100 Mbps. In the MII mode mii_tx_en and mii_txd will be sampled on the rising edge of the 25 MHz mii_tx_clk:
- In case of errors detection, mii_tx_er will be asserted and mii_txd dibits will be “01” for the rest of transmission to RMII interface.
- At a data rate of 10 Mbps (ref_clk frequency divided by 10), mii_txd will be sampled every
- RMII transmit transaction converted from MII transmit transaction at 100 Mbps. In the RMII mode rmii_tx_en and rmii_txd will be sampled on the rising edge of the 50 MHz ref_clk:
Software Support
Analog Devices recommends to use the provided software drivers.
References
resources/fpga/docs/util_mii_to_rmii.txt · Last modified: 21 Jul 2022 12:42 by Alin-Tudor Sferle