This version (12 Sep 2022 09:17) was approved by Alin-Tudor Sferle.The Previously approved version (20 Jul 2022 14:08) is available.
Table of Contents
CN0506 HDL Reference Design
A brief introduction of the acronyms that are going to be used:
- MII - media-independent interface
- RMII - reduced media-independent interface
- RGMII - reduced gigabit media-independent interface
- GMII - gigabit media-independent interface
- MAC - media access controller
- PHY - physical layer (ADIN1300 device)
Introduction
The CN0506 Dual PHY Ethernet evaluation board, is designed to interface the MAC and PHY through RGMII, MII or RMII interfaces.
On the RJ45 LAN socket, the status and speed LEDs are controlled from the FPGA. Each LED is bi-color(green or yellow), thus giving us 3 options: off, green or yellow for each LED. The right LED indicates the activity/status. It only uses the off or yellow options. The left LED indicates speed, off = 10Mbit, yellow = 100Mbit and green = 1Gbit. The speed information is obtain from the MAC, because the speed signals are not exposed by all interfaces, in some cases, the speed LEDs are hard coded to a maximum supported speed.
Default MAC to PHY interface is the RGMII one. To build a specific interface of the CN0506 evaluation board, you need to set the INTF_CFG environment variable to the desired one as follows:
hdl/projects/cn0506/zed> make INTF_CFG=MII
Management interface
A synchronous serial data interface similar to I2C is made from MDC and MDIO(bidirectional) signals.
MII interface
The MII interface is capable of supporting data rates of 100 Mbps and 10 Mbps.
The PHY sends a free-running clock as the receive clock(RX_CLK).
The transmit clock is also a free-running clock generated by the PHY.
Based on the link speed, the frequency of the Rx/Tx clock generated by the ADIN1300 is 25 MHz for 100 Mbit/s and 2.5 MHz for 10 Mbit/s.
Typically the PS/HPS MAC only exposes a GMII interface. But we can easily obtain the required MII signals. The MII being a subset of the GMII interface. The GMII contains the following extra signals:
- GTXCLK- Clock signal for gigabit TX signals(125MHz)
- an extra 4 MSBs, for both RXD and TXD data buses
The reset signal for both ADIN1300 comes from the PS/HPS.
There is an optional link_st signal, that indicates if a valid link is established. This signal is connected to the gpio[35] for PHY A and gpio[34] for PHY B.
The speed LEDs are hard coded to yellow(100Mbit).
Supported Carriers
-
- supported on FMC_A HPC(V57.1)
- connections PHY_A-EMAC1 and PHY_B-EMAC2
-
- supported on FMC HPC1
- connections to PS8. PHY_A-Ethernet0 and PHY_B-Ethernet1
-
- supported on FMC LPC
- connections to PS7. PHY_A-Ethernet0 and PHY_B-Ethernet1
-
- supported on FMC LPC
- connections to PS7. PHY_A-Ethernet0 and PHY_B-Ethernet1
RMII interface
The RMII interface is capable of supporting data rates of 100 Mbps and 10 Mbps. Its advantage over the MII is the reduced number of signals required.
The reference clock operates at 50MHz in both 100 Mbit/s and 10 Mbit/s mode. The software is used to configure the programmable clock oscillators on the board to 50MHz via I2C. In this design both the MAC(MII to RMII converter) and PHY work on the same 50MHz clock.
Software should not be used to set the ADIN1300 in the RMII mode, thus, this is done by setting the MAC_IF_SEL1(CRS_DV) and MAC_IF_SEL0 both to high, by using internal pull-up resistors in FPGA.
Because the REF_CLOCK is configured by software independently for each PHY, an independent reset signal is required for the initialization of each PHY. The main reset signal comes from the PS/HPS reset generator. But the software can reset independently, the PHY A by setting high the gpio[37] and the PHY B by setting high the gpio[36]. The mentioned GPIOs are controlled by the PS/HPS.
The speed LEDs are hard coded to 100Mbit.
Supported Carriers
-
- supported on FMC HPC1
- connections to PS8. PHY_A-Ethernet0 and PHY_B-Ethernet1
-
- supported on FMC LPC
- connections to PS7. PHY_A-Ethernet0 and PHY_B-Ethernet1
-
- supported on FMC LPC
- connections to PS7. PHY_A-Ethernet0 and PHY_B-Ethernet1
RGMII interface
The RGMII interface is capable of supporting data rates of 1 Gbps, 100 Mbps, and 10 Mbps. The benefit of the RGMII over GMII, is that the RGMII consists only of 12 pins, as opposed to GMII's 24.
Source synchronous interfaces are used for both RX and TX.
The ADIN1300 generates a 125 MHz, 25 MHz, or 2.5 MHz RXC signal to synchronize the RXD pins.
The transmit clock signal is provided by the MAC on the TXC line.
The reset signal for both adin1300 comes from the PS/HPS.
The INT_N is not used as an interrupt, it is only monitored by software as input on gpio[33] (PHY A) and gpio[32] (PHY B).
The speed LEDs are fully functional for the RGMII interface.
Particularly for the Xilinx carriers, the GMII to RGMII converters use shared resources(clock resources). This option does not affect in any way the independence of the two interfaces to each other.
Supported Carriers
-
- supported on FMC HPC1
- connections to PS8. PHY_A-Ethernet0 and PHY_B-Ethernet1
-
- supported on FMC LPC
- connections to PS7. PHY_A-Ethernet0 and PHY_B-Ethernet1
-
- supported on FMC LPC
- connections to PS7. PHY_A-Ethernet0 and PHY_B-Ethernet1
More related info:
Help & Support
- The HDL user guide contains all the documentation, build instructions and register map tables.
- The following quick links allows you to browse the github repository for a list of current branches, library components, and projects.
- Questions? We can help with FPGA questions, Linux driver questions.
resources/eval/user-guides/circuits-from-the-lab/cn0506/hdl.txt · Last modified: 12 Sep 2022 09:17 by Alin-Tudor Sferle