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resources:fpga:docs:util_extract [11 Oct 2021 14:57] Iulia Moldovan Edit footer |
resources:fpga:docs:util_extract [13 Oct 2021 08:33] Iulia Moldovan Edit footer |
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| - | ===== UTIL_EXTRACT ===== | + | ====== UTIL_EXTRACT ====== |
| The UTIL_EXTRACT IP allows the extraction of the trigger signal and restoration of the data signal that was embedded in the data stream by the AXI_ADC_TRIGGER IP. | The UTIL_EXTRACT IP allows the extraction of the trigger signal and restoration of the data signal that was embedded in the data stream by the AXI_ADC_TRIGGER IP. | ||
| - | ==== Configuration Parameters ==== | + | |
| + | ===== Configuration Parameters ===== | ||
| ^ Name ^ Description ^ Default Value^ | ^ Name ^ Description ^ Default Value^ | ||
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| | ''DATA_WIDTH'' | Data width. It assumes the trigger is in bit (n*16)-1, with n being the channel number | NUM_OF_CHANNELS * 16 | | | ''DATA_WIDTH'' | Data width. It assumes the trigger is in bit (n*16)-1, with n being the channel number | NUM_OF_CHANNELS * 16 | | ||
| - | ==== Interface ==== | + | |
| + | ===== Interface ===== | ||
| ^ Interface ^ Pin ^ Type ^ Description ^ | ^ Interface ^ Pin ^ Type ^ Description ^ | ||
| Line 22: | Line 24: | ||
| | | ''trigger_out'' | ''output'' | Trigger output. Is an logic OR of the triggers from all the channels that are captured simulaneously | | | | ''trigger_out'' | ''output'' | Trigger output. Is an logic OR of the triggers from all the channels that are captured simulaneously | | ||
| - | ==== References ==== | + | |
| + | ===== References ===== | ||
| * [[https://github.com/analogdevicesinc/hdl/tree/master/library/util_extract | UTIL_EXTRACT IP source code]] \\ | * [[https://github.com/analogdevicesinc/hdl/tree/master/library/util_extract | UTIL_EXTRACT IP source code]] \\ | ||
| * [[/resources/fpga/docs/arch | ADI Reference designs architecture ]] \\ | * [[/resources/fpga/docs/arch | ADI Reference designs architecture ]] \\ | ||
| - | {{navigation HDL User Guide#axi_ip|AXI IP cores#hdl|Main page#tips|Using and modifying the HDL design}} | + | {{navigation HDL User Guide#ip_cores|IP cores#hdl|Main page#tips|Using and modifying the HDL design}} |
resources/fpga/docs/util_extract.txt · Last modified: 13 Oct 2021 08:33 by Iulia Moldovan