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--- resources:fpga:docs:axi_ltc2387 [27 Sep 2022 15:16] – Add link to HDL architecture Iulia Moldovan
+++ resources:fpga:docs:axi_ltc2387 [22 Feb 2023 18:18] (current) – Added note about one lane restrictions Iulia Moldovan
@@ Line 74: / Line 74: @@
 == ADC_DATA ==
-Depending on ''TWOLANES'' parameter, whether it is set or not, the output adc_data is either taken from the DA+/- port interleaved with bits from DB+/-, or it is taken only from DA+/- port. \\
+Depending on ''TWOLANES'' parameter, whether it is set or not, the output //adc_data// is either taken from the DA+/- port interleaved with bits from DB+/-, or it is taken only from DA+/- port. \\
+<note>Note that when using the **ONE LANE** configuration, the only resolution available is **18 bits**!</note>
 ==== Channel module description ====

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