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The axi_ltc2387 IP core interfaces to the LTC2387-16 and LTC2387-18 devices. This documentation only covers the IP core and requires that one must be familiar with the device for a complete and better understanding.

More about the generic framework interfacing ADCs can be read here: axi_adc_ip, and about our architecture here.


  • AXI Slave Memory Mapped control/status interface
  • Select between the 16-bit or 18-bit design
  • Supported only on Xilinx devices


Name Description Default Value
ID Core ID should be unique for each LTC2387 IP in the system 0
FPGA_TECHNOLOGY Encoded value describing the technology/generation of the FPGA device (arria 10/7series) set automatically
FPGA_FAMILY Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT) set automatically
SPEED_GRADE Encoded value describing the FPGA's speed-grade set automatically
DEV_PACKAGE Encoded value describing the device package. The package might affect high-speed interfaces set automatically
IO_DELAY_GROUP The delay group name which is set for the delay controller “adc_if_delay_group”
IO_DELAY_CTRL Can have the values 0 or 1, conditioning the instantiation of the IODELAY_CTRL primitive. You can place only one IODELAY_CTRL per I/O bank, and need to set the same IO_DELAY_GROUP for the interfaces placed in that I/O bank. 1
DELAY_REFCLK_FREQUENCY Reference clock frequency used for ad_data_in instances 200
USERPORTS_DISABLE If set, indicates that the logic related to the User Data Format (e.g. decimation) was not implemented. (as a result of a configuration of the IP instance) 0
DATAFORMAT_DISABLE Disable the Data Format control module 0
ADC_INIT_DELAY Initial delay 22
ADC_RES The ADC's resolution. Can be 16/18 bits. 16
OUT_RES The output data resolution. Can be 16/18 bits. 16
TWOLANES Specifies whether the two-lane output mode is activated or not. When activated, the ADC outputs two bits at the same time, on DA+/DA- and DB+/DB-. When it is low, then DB+/DB- is disabled. 1

I/O Interface

Interface Pin Type Description
Delay Clock
delay_clk input Delay clock input for IO_DELAY control, connect to 200MHz clock
LVDS ADC interface
ref_clk input LVDS input clock
clk_gate input Signal enabling CLK+/CLK-
dco_* input LVDS data clock input
da_* input Serial LVDS data input
db_* input Serial LVDS data input
DMA ADC interface
adc_valid output Indicates valid data at the current channel
adc_data output[OUT_RES-1:0] Received data output
adc_dovf input Data overflow, must be connected to the DMA
AXI_S_MM interface
s_axi_* Standard AXI Slave Memory Map interface

Detailed description

From the HDL perspective, the selection between LTC2387-16 and LTC2387-18 is done by the ADC_RES and OUT_RES parameters for the modules.

  • For LTC2387-16 is ADC_RES = 16, and OUT_RES = 16
  • For LTC2387-18 is ADC_RES = 18, and OUT_RES = 32 (because the addresses are on a number of bits that's power of 2)

Internal interface description

The LVDS interface module has as inputs the LVDS signals for clock and data:


LVDS clock input; it is an echoed version of the CLK+/CLK- signal, and it's used to latch the data outputs from the chip.

DA+/DA- and DB+/DB-

Serial LVDS data inputs; DB+/- is used only when TWOLANES parameter is active


This signal clk_gate is enabling the CLK+/CLK- which is driven by the reference clock. It is generated by AXI_PWM_GEN.


It is 1 for the current sample that is sent. This is generated depending on clk_gate.


Depending on TWOLANES parameter, whether it is set or not, the output adc_data is either taken from the DA+/- port interleaved with bits from DB+/-, or it is taken only from DA+/- port.

Channel module description

Here it's where the expected pattern is created and checked if the data received from the DMA is the correct one (this is used for quick validation of the design).
In the case of the device with 16-bit resolution, a sign extension is done here also.

Register Map

Address Name Description
0x0000 0x0000 BASE See the Base (common to all cores) table for more detail
0x0000 0x0000 RX COMMON See the ADC Common table for more detail
0x0000 0x0000 RX CHANNELS See the ADC Channel table for more detail

Base (common to all cores)

Click to expand regmap

ADC Common (axi_ad*)

Click to expand regmap

ADC Channel (axi_ad*)

Click to expand regmap

Software Guidelines

The software parts for this IP core can be found at:


resources/fpga/docs/axi_ltc2387.1664284573.txt.gz · Last modified: 27 Sep 2022 15:16 by Iulia Moldovan