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resources:fpga:docs:axi_clkgen [11 Oct 2021 14:55] Iulia Moldovan Edit next page to be Using and modifying the HDL design |
resources:fpga:docs:axi_clkgen [12 Oct 2021 16:45] Iulia Moldovan Edit title |
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| - | ===== AXI_CLKGEN IP core ===== | + | ====== AXI CLKGEN IP core ====== |
| The [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_clkgen|axi_clkgen]] IP core is a software programmable clock generator. | The [[https://github.com/analogdevicesinc/hdl/tree/master/library/axi_clkgen|axi_clkgen]] IP core is a software programmable clock generator. | ||
| - | ==== Block Diagram ==== | + | |
| + | ===== Block Diagram ===== | ||
| {{ :resources:fpga:docs:axi_clkgen_1.svg | AXI_CLKGEN Block diagram }} | {{ :resources:fpga:docs:axi_clkgen_1.svg | AXI_CLKGEN Block diagram }} | ||
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| The register map allows resetting the MMCM, changing the clock source, checking the status of the MMCM lock and controlling the DRP interface. | The register map allows resetting the MMCM, changing the clock source, checking the status of the MMCM lock and controlling the DRP interface. | ||
| - | ==== Configuration Parameter ==== | + | |
| + | ===== Configuration Parameters ===== | ||
| ^ Name ^ Description ^ Default Value^ | ^ Name ^ Description ^ Default Value^ | ||
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| | ''CLK1_DIV'' | CLKOUT1_DIVIDE MMCM parameter | 6 | | | ''CLK1_DIV'' | CLKOUT1_DIVIDE MMCM parameter | 6 | | ||
| | ''CLK1_PHASE'' | CLKOUT1_PHASE MMCM parameter | 0.000 | | | ''CLK1_PHASE'' | CLKOUT1_PHASE MMCM parameter | 0.000 | | ||
| - | ==== Signal and Interface Pins ==== | + | |
| + | |||
| + | ===== Signal and Interface Pins ===== | ||
| ^ Interface ^ Pin ^ Type ^ Description ^ | ^ Interface ^ Pin ^ Type ^ Description ^ | ||
| - | | '' Clocks'' | **Input and output clocks** ||| | + | | '' Clocks'' | **Input and output clocks** ||| |
| - | | | ''clk'' | ''input'' | Reference clock 1 | | + | | | ''clk'' | ''input'' | Reference clock 1 | |
| - | | | ''clk2'' | ''input'' | Reference clock 2 | | + | | | ''clk2'' | ''input'' | Reference clock 2 | |
| - | | | ''clk_0'' | ''output'' | Output clock 0 | | + | | | ''clk_0'' | ''output'' | Output clock 0 | |
| - | | | ''clk_1'' | ''output'' | Output clock 1 | | + | | | ''clk_1'' | ''output'' | Output clock 1 | |
| - | | ''s axi '' | **AXI Slave Memory Map interface** ||| | + | | ''s_axi '' | **AXI Slave Memory Map interface** ||| |
| + | |||
| + | |||
| + | ===== Register Map ===== | ||
| - | ==== Register Map ==== | ||
| {{page>:resources:fpga:docs:hdl:regmap##Base (common to all cores)&nofooter&noeditbtn}} | {{page>:resources:fpga:docs:hdl:regmap##Base (common to all cores)&nofooter&noeditbtn}} | ||
| {{page>:resources:fpga:docs:hdl:regmap##Clock Generator (axi_clkgen)&nofooter&noeditbtn}} | {{page>:resources:fpga:docs:hdl:regmap##Clock Generator (axi_clkgen)&nofooter&noeditbtn}} | ||
| + | |||
| ===== References ===== | ===== References ===== | ||
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| * [[xilinx>support/documentation/application_notes/xapp888_7Series_DynamicRecon.pdf|MMCM and PLL Dynamic Reconfiguration]] | * [[xilinx>support/documentation/application_notes/xapp888_7Series_DynamicRecon.pdf|MMCM and PLL Dynamic Reconfiguration]] | ||
| - | {{navigation HDL User Guide#axi_ip|AXI IP cores#hdl|Main page#tips|Using and modifying the HDL design}} | + | {{navigation HDL User Guide#ip_cores|IP cores#hdl|Main page#tips|Using and modifying the HDL design}} |
resources/fpga/docs/axi_clkgen.txt · Last modified: 12 Oct 2021 16:45 by Iulia Moldovan