The axi_ad9671 IP core can be used to interface the AD9671 Octal Ultrasound AFE with digital demodulator.
An AXI Memory Map interface is used for configuration. Data is received from Xilinx JESD IP.
More about the generic framework interfacing ADCs can be read here: axi_adc_ip.
| ||Core ID should be unique for each AD9671 IP in the system. ID 0 is master||0|
| ||Selection between Xilinx(0) and Altera(1) devices||0|
| ||Selects if 4 lanes (1) or 2 lanes (0) are connected||1|
| ||Data to be connected to the JESD core|
| || ||JESD clock rate / 40|
| || ||RX data from the JESD core. 128 bit wide for QUAD operation, and 64 bit for DUAL operation|
| || |
| || ||Placeholder for interfaces. Assume data is always valid|
| || ||Always ready|
| || |
| ||AXI Slave Memory Map interface|
| ||FIFO interface for connecting to the DMA|
| || ||Loopback of the tx_clk. most of the modules of the core run on this clock|
| || ||ADC valid, used to read new data from the DMA. Each bit applies to one channel|
| || ||Set when the channel is enabled, activated by software. Each bit applies to one channel|
| || ||Data for all channels|
| || ||Data overflow input|
| || ||Data underflow input.|
| ||Synchronization between multiples cores|
| || ||Starts the synchronization procedure. Comes from the master IP|
| || ||Starts the synchronization procedure. Sent to the slave IPs|
| || ||Read address. All IPs are sending data from the same memory location. Comes from the master IP|
| || ||Read address. All IPs are sending data from the same memory location. Sent to the slave IPs|
The top module, axi_ad9671, instantiates:
The interface module, axi_ad9671_if, takes the data from the Xilinx JESD IP and splits it into channels. In order to synchronize several AD9671 chips, a FIFO is used and a comparison mechanism with a start code.
The data from the interface module is processed by the adc channel module.
The channel module implements:
The control of the AD9671 chip is done through a SPI interface, which is needed at system level.
The design should use a DMA to move the data from the output of the IP to memory.
If the data needs to be processed in HDL before moved to the memory, it can be done at the output of the IP (at system level) or inside of the adc channel module (at IP level).