This version (13 Oct 2021 10:53) was approved by Adrian Costina.The Previously approved version (11 Oct 2021 14:41) is available.Diff

AXI_AD9671 IP core

The axi_ad9671 IP core can be used to interface the AD9671 Octal Ultrasound AFE with digital demodulator. An AXI Memory Map interface is used for configuration. Data is received from Xilinx JESD IP.

More about the generic framework interfacing ADCs can be read here: axi_adc_ip.


  • AXI based configuration
  • PRBS monitoring (PN9 and PN23)
  • Altera Quartus compatible
  • Xilinx Vivado compatible

Block Diagram

Configuration Parameter

Name Description Default Value
ID Core ID should be unique for each AD9671 IP in the system. ID 0 is master 0
DEVICE_TYPE Selection between Xilinx(0) and Altera(1) devices 0
QUAD_OR_DUAL_N Selects if 4 lanes (1) or 2 lanes (0) are connected 1


Interface Pin Type Description
jesd interface Data to be connected to the JESD core
rx_clk* input JESD clock rate / 40
rx_data input[127/63:0] RX data from the JESD core. 128 bit wide for QUAD operation, and 64 bit for DUAL operation
rx_sof* input[3:0]
rx_valid input Placeholder for interfaces. Assume data is always valid
rx_ready output Always ready
rx_sof* input[3:0]
s axi AXI Slave Memory Map interface
dma interface FIFO interface for connecting to the DMA
adc_clk output Loopback of the tx_clk. most of the modules of the core run on this clock
adc_valid output[7:0] ADC valid, used to read new data from the DMA. Each bit applies to one channel
adc_enable output[7:0] Set when the channel is enabled, activated by software. Each bit applies to one channel
adc_data input[127:0] Data for all channels
adc_dovf input Data overflow input
adc_dunf input Data underflow input.
sync interface Synchronization between multiples cores
adc_sync_in input Starts the synchronization procedure. Comes from the master IP
adc_sync_out output Starts the synchronization procedure. Sent to the slave IPs
adc_raddr_in input[3:0] Read address. All IPs are sending data from the same memory location. Comes from the master IP
adc_raddr_out output[3:0] Read address. All IPs are sending data from the same memory location. Sent to the slave IPs

Detailed Architecture

Detailed Description

The top module, axi_ad9671, instantiates:

  • the interface module
  • the channel processing module
  • the ADC common register map
  • the AXI handling interface

The interface module, axi_ad9671_if, takes the data from the Xilinx JESD IP and splits it into channels. In order to synchronize several AD9671 chips, a FIFO is used and a comparison mechanism with a start code.

The data from the interface module is processed by the adc channel module.
The channel module implements:

  • a PRBS monitor
  • data format conversion
  • the ADC CHANNEL register map

Register Map

Base (common to all cores)

Click to expand regmap

ADC Common (axi_ad*)

Click to expand regmap

ADC Channel (axi_ad*)

Click to expand regmap

Design Guidelines

The control of the AD9671 chip is done through a SPI interface, which is needed at system level.

The design should use a DMA to move the data from the output of the IP to memory.

If the data needs to be processed in HDL before moved to the memory, it can be done at the output of the IP (at system level) or inside of the adc channel module (at IP level).


resources/fpga/docs/axi_ad9671.txt · Last modified: 13 Oct 2021 09:48 by Iulia Moldovan