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AXI_AD9371

The axi_ad9371 IP core interfaces to the AD9371 device. This documentation only covers the IP core and requires that one must be familiar with the device for a complete and better understanding.

Features

AXI Lite control/status interface
Hardware and software DC filtering
IQ correction
Internal DDS
Receive and transmit loopback
Supports both Altera and Xilinx devices

Block Diagram

Functional Description

The axi_ad9371 cores architecture contains:

Interface module, which implements the application layer of the JESD20B interface. This interface is connected to the JESD204B IP core.
Receive module, which contains:
- ADC channel processing modules, one for each channel (receive path supports 4 channels)
  - data processing modules (DC filter, IQ Correction and Data format control)
  - ADC Channel register map
- ADC Common register map
Observation module, which has the same architecture as the Receive module, but supports just 2 channels
Transmit module, which contains:
- DAC channel processing modules, one for each channel
  - Different data generators (DDS, pattern)
  - IQ Correction
  - DAC Channel register map
- Delay Control and DAC Common register map
AXI to uP interface wrapper modules. You can find information about the uP interface here.

Interface Description

The interface module of the core is connected to the JESD204B IP core and does a simple realignment of the data stream.

Parameters

Name	Description	Default Value
`ID`	Core ID should be unique for each ad9371 IP in the system	0
`DEVICE_TYPE`	Used to select between 7 Series (0), Virtex 6 (1) or Ultrascale (2) for Xilinx devices	0
`ADC_DATAPATH_DISABLE`	Disable the receive data path modules.	0
`DAC_DATAPATH_DISABLE`	Disable the transmit data path modules.	0

I/O interface and signals

Interface	Pin	Type	Description
Receive interface from JESD204B IP
	`adc_clk`	`input`	Rx core clock from the GTs, in general clock rate is (Lane Rate)/40.
	`adc_rx_valid`	`input`	This signal is unused; is defined just to make tools happy.
	`adc_rx_sof`	`input[3:0]`	Frame boundary indication signals. Indicate the byte position of the first byte of a frame.
	`adc_rx_data`	`input[63:0]`	Received data stream from the JESD204B IP.
	`adc_rx_ready`	`output`	This signal is tied to one; is defined just to make tools happy.
Observation receive interface from JESD204B IP
	`adc_os_clk`	`input`	Rx core clock from the GTs, in general clock rate is (Lane Rate)/40.
	`adc_rx_os_valid`	`input`	This signal is unused; is defined just to make tools happy.
	`adc_rx_os_sof`	`input[3:0]`	Frame boundary indication signals. Indicate the byte position of the first byte of a frame.
	`adc_rx_os_data`	`input[63:0]`	Received data stream from the JESD204B IP.
	`adc_rx_os_ready`	`output`	This signal is tied to one; is defined just to make tools happy.
Transmit interface to JESD204B IP
	`dac_clk`	`input`	Tx core clock from the GTs, in general clock rate is (Lane Rate)/40.
	`dac_tx_valid`	`output`	This signal is tied to one; is defined just to make tools happy.
	`dac_tx_data`	`output[63:0]`	Transmitted data stream to the JESD204B IP.
	`dac_tx_ready`	`input`	This signal is not used; is defined just to make tools happy.
Transmit master/slave
	`dac_sync_in`	`input`	Synchronization signal of the transmit path for slave devices (ID>0)
	`dac_sync_out`	`output`	Synchronization signal of the transmit path for master device (ID==0)
Receive FIFO interface (for DMA)
	`adc_enable_*`	`output`	If set, the channel is enabled (one for each channel)
	`adc_valid_*`	`output`	Indicates valid data at the current channel (one for each channel)
	`adc_data_*`	`output[15:0]`	Received data output (one for each channel)
	`adc_dovf`	`input`	Data overflow, must be connected to the DMA
	`adc_dunf`	`input`	Data underflow, must be connected to the DMA
Observation FIFO interface (for DMA)
	`adc_os_enable_*`	`output`	If set, the channel is enabled (one for each channel)
	`adc_os_valid_*`	`output`	Indicates valid data at the current channel (one for each channel)
	`adc_os_data_*`	`output[31:0]`	Received data output (one for each channel)
	`adc_os_dovf`	`input`	Data overflow, must be connected to the DMA
	`adc_os_dunf`	`input`	Data underflow, must be connected to the DMA
Transmit FIFO interface (for DMA)
	`dac_enable_*`	`output`	If set, the channel is enabled (one for each channel)
	`dac_valid_*`	`output`	Indicates valid data request at the current channel (one for each channel)
	`dac_data_*`	`input[31:0]`	Transmitted data output (one for each channel)
	`dac_dovf`	`input`	Data overflow, must be connected to the DMA
	`dac_dunf`	`input`	Data underflow, must be connected to the DMA
AXI Slave Memory Mapped interface
	`s_axi_*`		Standard AXI Slave Memory Map interface

Register Map

The register map of the core contains instances of several generic register maps like ADC common, ADC channel, DAC common, DAC channel etc. The following table presents the base addresses of each instance, after that can be found the detailed description of each generic register map. The absolute address of a register should be calculated by adding the instance base address to the registers relative address.

Register Map base addresses for axi_ad9371

0x0000	0x0000	BASE	See the Base (common to all cores) table for more detail
Address		Name	Description
DWORD	BYTE	Name	Description
0x0010	0x0040	RX COMMON	See the ADC Common table for more detail
0x0080	0x0200	ADC TPL	See the JESD TPL table for more detail
0x0100	0x0400	RX CHANNELS	See the ADC Channel table for more detail
0x1010	0x4040	TX COMMON	See the DAC Common table for more detail
0x1080	0x4200	DAC TPL	See the JESD TPL table for more detail
0x1100	0x4400	TX CHANNELS	See the DAC Channel table for more detail
0x2100	0x8400	RX OS CHANNELS	See the ADC Channel table for more detail

Base (common to all cores)

Click to expand regmap

0x0000	0x0000	REG_VERSION				Version and Scratch Registers
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[31:0]	VERSION[31:0]	RO	0x00000000	Version number. Unique to all cores.
0x0001	0x0004	REG_ID				Version and Scratch Registers
		[31:0]	ID[31:0]	RO	0x00000000	Instance identifier number.
0x0002	0x0008	REG_SCRATCH				Version and Scratch Registers
		[31:0]	SCRATCH[31:0]	RW	0x00000000	Scratch register.
0x0003	0x000c	REG_CONFIG				Version and Scratch Registers
		[0]	IQCORRECTION_DISABLE	RO	0x0	If set, indicates that the IQ Correction module was not implemented. (as a result of a configuration of the IP instance)
		[1]	DCFILTER_DISABLE	RO	0x0	If set, indicates that the DC Filter module was not implemented. (as a result of a configuration of the IP instance)
		[2]	DATAFORMAT_DISABLE	RO	0x0	If set, indicates that the Data Format module was not implemented. (as a result of a configuration of the IP instance)
		[3]	USERPORTS_DISABLE	RO	0x0	If set, indicates that the logic related to the User Data Format (e.g. decimation) was not implemented. (as a result of a configuration of the IP instance)
		[4]	MODE_1R1T	RO	0x0	If set, indicates that the core was implemented in 1 channel mode. (e.g. refer to AD9361 data sheet)
		[5]	DELAY_CONTROL_DISABLE	RO	0x0	If set, indicates that the delay control is disabled for this IP. (as a result of a configuration of the IP instance)
		[6]	DDS_DISABLE	RO	0x0	If set, indicates that the DDS is disabled for this IP. (as a result of a configuration of the IP instance)
		[7]	CMOS_OR_LVDS_N	RO	0x0	CMOS or LVDS mode is used for the interface. (as a result of a configuration of the IP instance)
		[8]	PPS_RECEIVER_ENABLE	RO	0x0	If set, indicates the PPS receiver is enabled. (as a result of a configuration of the IP instance)
		[9]	SCALECORRECTION_ONLY	RO	0x0	If set, indicates that the IQ Correction module implements only scale correction. IQ correction must be enabled. (as a result of a configuration of the IP instance)
		[12]	EXT_SYNC	RO	0x0	If set the transport layer cores (ADC/DAC) have implemented the support for external synchronization signal.
		[13]	RD_RAW_DATA	RO	0x0	If set, the ADC has the capability to read raw data in register REG_CHAN_RAW_DATA from adc_channel.
0x0004	0x0010	REG_PPS_IRQ_MASK				PPS Interrupt mask
		[0]	PPS_IRQ_MASK	RW	0x1	Mask bit for the 1PPS receiver interrupt
0x0007	0x001c	REG_FPGA_INFO				FPGA device information Intel encoded values Xilinx encoded values
		[31:24]	FPGA_TECHNOLOGY	RO	0x0	Encoded value describing the technology/generation of the FPGA device (arria 10/7series)
		[23:16]	FPGA_FAMILY	RO	0x0	Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT or zynq, kintex, virtex)
		[15:8]	SPEED_GRADE	RO	0x0	Encoded value describing the FPGA's speed-grade
		[7:0]	DEV_PACKAGE	RO	0x0	Encoded value describing the device package. The package might affect high-speed interfaces
Tue Mar 14 10:17:59 2023

ADC Common (axi_ad*)

Click to expand regmap

0x0010	0x0040	REG_RSTN				ADC Interface Control & Status
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[2]	CE_N	RW	0x0	Clock enable, default is enabled(0x0). An inverse version of the signal is exported out of the module to control clock enables
		[1]	MMCM_RSTN	RW	0x0	MMCM reset only (required for DRP access). Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
		[0]	RSTN	RW	0x0	Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
0x0011	0x0044	REG_CNTRL				ADC Interface Control & Status
		[16]	SDR_DDR_N	RW	0x0	Interface type (1 represents SDR, 0 represents DDR)
		[15]	SYMB_OP	RW	0x0	Select symbol data format mode (0x1)
		[14]	SYMB_8_16B	RW	0x0	Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b)
		[12:8]	NUM_LANES[4:0]	RW	0x0	Number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane). For AD7768, AD7768-4 and AD777x number of active lanes : 1/2/4/8 where supported.
		[3]	SYNC	RW	0x0	Initialize synchronization between multiple ADCs
		[2]	R1_MODE	RW	0x0	Select number of RF channels 1 (0x1) or 2 (0x0).
		[1]	DDR_EDGESEL	RW	0x0	Select rising edge (0x0) or falling edge (0x1) for the first part of a sample (if applicable) followed by the successive edges for the remaining parts. This only controls how the sample is delineated from the incoming data post DDR registers.
		[0]	PIN_MODE	RW	0x0	Select interface pin mode to be clock multiplexed (0x1) or pin multiplexed (0x0). In clock multiplexed mode, samples are received on alternative clock edges. In pin multiplexed mode, samples are interleaved or grouped on the pins at the same clock edge.
0x0012	0x0048	REG_CNTRL_2				ADC Interface Control & Status
		[1]	EXT_SYNC_ARM	RW	0x0	Setting this bit will arm the trigger mechanism sensitive to an external sync signal. Once the external sync signal goes high it synchronizes channels within a ADC, and across multiple instances. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.
		[2]	EXT_SYNC_DISARM	RW	0x0	Setting this bit will disarm the trigger mechanism sensitive to an external sync signal. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.
		[8]	MANUAL_SYNC_REQUEST	RW	0x0	Setting this bit will issue an external sync event if it is hooked up inside the fabric. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.
0x0013	0x004c	REG_CNTRL_3				ADC Interface Control & Status
		[8]	CRC_EN	RW	0x0	Setting this bit will enable the CRC generation.
		[7:0]	CUSTOM_CONTROL	RW	0x00	ADAQ8092 Select output format decode mode. - bit [0] - enables digital output randomizer decode - bit [1] - enables alternate bit polarity decode AD4858 Select data format/oversampling - bit [2] - enable oversampling - bits [1:0] packet format selection: 0 = 20 bit 1 = 24 bit 2 = 32 bit 3 = 32 bit AD7606X_PI Select the parallel interface's operation mode - bit [2] - change mode with the selected one - bits [1:0] - requested operation mode: 0 = SIMPLE 1 = CRC_ENABLED 2 = STATUS_HEADER 3 = CRC_STATUS 07 Mar 2023 17:38 · Andrei Grozav
0x0015	0x0054	REG_CLK_FREQ				ADC Interface Control & Status
		[31:0]	CLK_FREQ[31:0]	RO	0x0000	Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock.
0x0016	0x0058	REG_CLK_RATIO				ADC Interface Control & Status
		[31:0]	CLK_RATIO[31:0]	RO	0x0000	Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
0x0017	0x005c	REG_STATUS				ADC Interface Control & Status
		[4]	ADC_CTRL_STATUS	RO	0x0	If set, indicates that the device's register data is available on the data bus.
		[3]	PN_ERR	RO	0x0	If set, indicates pn error in one or more channels.
		[2]	PN_OOS	RO	0x0	If set, indicates pn oos in one or more channels.
		[1]	OVER_RANGE	RO	0x0	If set, indicates over range in one or more channels.
		[0]	STATUS	RO	0x0	Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores.
0x0018	0x0060	REG_DELAY_CNTRL				ADC Interface Control & Status(`Deprecated from version 9`)
		[17]	DELAY_SEL	RW	0x0	Delay select, a 0x0 to 0x1 transition in this register initiates a delay access controlled by the registers below.
		[16]	DELAY_RWN	RW	0x0	Delay read (0x1) or write (0x0), the delay is accessed directly (no increment or decrement) with an address corresponding to each pin, and data corresponding to the total delay.
		[15:8]	DELAY_ADDRESS[7:0]	RW	0x00	Delay address, the range depends on the interface pins, data pins are usually at the lower range.
		[4:0]	DELAY_WDATA[4:0]	RW	0x0	Delay write data, a value of 1 corresponds to (1/200)ns for most devices.
0x0019	0x0064	REG_DELAY_STATUS				ADC Interface Control & Status(`Deprecated from version 9`)
		[9]	DELAY_LOCKED	RO	0x0	Indicates delay locked (0x1) state. If this bit is read 0x0, delay control has failed to calibrate the elements.
		[8]	DELAY_STATUS	RO	0x0	If set, indicates busy status (access pending). The read data may not be valid if this bit is set.
		[4:0]	DELAY_RDATA[4:0]	RO	0x0	Delay read data, current delay value in the elements
0x001A	0x0068	REG_SYNC_STATUS				ADC Synchronization Status register
		[0]	ADC_SYNC	RO	0x0	ADC synchronization status. Will be set to 1 after the synchronization has been completed or while waiting for the synchronization signal in JESD204 systems.
0x001C	0x0070	REG_DRP_CNTRL				ADC Interface Control & Status
		[28]	DRP_RWN	RW	0x0	DRP read (0x1) or write (0x0) select (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
		[27:16]	DRP_ADDRESS[11:0]	RW	0x00	DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
		[15:0]	RESERVED[15:0]	RO	0x0000	Reserved for backward compatibility.
0x001D	0x0074	REG_DRP_STATUS				ADC Interface Control & Status
		[17]	DRP_LOCKED	RO	0x0	If set indicates that the DRP has been locked.
		[16]	DRP_STATUS	RO	0x0	If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
		[15:0]	RESERVED[15:0]	RO	0x00	Reserved for backward compatibility.
0x001E	0x0078	REG_DRP_WDATA				ADC DRP Write Data
		[15:0]	DRP_WDATA[15:0]	RW	0x00	DRP write data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
0x001F	0x007c	REG_DRP_RDATA				ADC DRP Read Data
		[15:0]	DRP_RDATA[15:0]	RO	0x00	DRP read data (does not include GTX lanes).
0x0020	0x0080	REG_ADC_CONFIG_WR				ADC Write Configuration Data
		[31:0]	ADC_CONFIG_WR[31:0]	RW	0x0000	Custom Write to the available registers.
0x0021	0x0084	REG_ADC_CONFIG_RD				ADC Read Configuration Data
		[31:0]	ADC_CONFIG_RD[31:0]	RO	0x0000	Custom read of the available registers.
0x0022	0x0088	REG_UI_STATUS				User Interface Status
		[2]	UI_OVF	RW1C	0x0	User Interface overflow. If set, indicates an overflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.
		[1]	UI_UNF	RW1C	0x0	User Interface underflow. If set, indicates an underflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.
		[0]	UI_RESERVED	RW1C	0x0	Reserved for backward compatibility.
0x0023	0x008c	REG_ADC_CONFIG_CTRL				ADC RD/WR configuration
		[31:0]	ADC_CONFIG_CTRL[31:0]	RW	0x0000	Control RD/WR requests to the device's register map: bit 1 - RD ('b1) , WR ('b0), bit 0 - enable WR/RD operation.
0x0028	0x00a0	REG_USR_CNTRL_1				ADC Interface Control & Status
		[7:0]	USR_CHANMAX[7:0]	RW	0x00	This indicates the maximum number of inputs for the channel data multiplexers. User may add different processing modules post data capture as another input to this common multiplexer. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
0x0029	0x00a4	REG_ADC_START_CODE				ADC Synchronization start word
		[31:0]	ADC_START_CODE[31:0]	RW	0x00000000	This sets the startcode that is used by the ADCs for synchronization NOT-APPLICABLE if START_CODE_DISABLE is set (0x1).
0x002E	0x00b8	REG_ADC_GPIO_IN				ADC GPIO inputs
		[31:0]	ADC_GPIO_IN[31:0]	RO	0x00000000	This reads auxiliary GPI pins of the ADC core
0x002F	0x00bc	REG_ADC_GPIO_OUT				ADC GPIO outputs
		[31:0]	ADC_GPIO_OUT[31:0]	RW	0x00000000	This controls auxiliary GPO pins of the ADC core NOT-APPLICABLE if GPIO_DISABLE is set (0x1).
0x0030	0x00c0	REG_PPS_COUNTER				PPS Counter register
		[31:0]	PPS_COUNTER[31:0]	RO	0x00000000	Counts the core clock cycles (can be a device clock or interface clock) between two 1PPS pulse.
0x0031	0x00c4	REG_PPS_STATUS				PPS Status register
		[0]	PPS_STATUS	RO	0x0	If this bit is asserted there is no incomming 1PPS signal. Maybe the source is out of sync or it's not active.
Fri Aug 11 18:29:53 2023

ADC Channel (axi_ad*)

Click to expand regmap

0x0100	0x0400	REG_CHAN_CNTRL				ADC Interface Control & Status
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[11]	ADC_LB_OWR	RW	0x0	If set, forces ADC_DATA_SEL to 1, enabling data loopback
		[10]	ADC_PN_SEL_OWR	RW	0x0	If set, forces ADC_PN_SEL to 0x9, device specific pn (e.g. ad9361) If both ADC_PN_TYPE_OWR and ADC_PN_SEL_OWR are set, they are ignored
		[9]	IQCOR_ENB	RW	0x0	if set, enables IQ correction or scale correction. NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
		[8]	DCFILT_ENB	RW	0x0	if set, enables DC filter (to disable DC offset, set offset value to 0x0). NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).
		[6]	FORMAT_SIGNEXT	RW	0x0	if set, enables sign extension (applicable only in 2's complement mode). The data is always sign extended to the nearest byte boundary. NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).
		[5]	FORMAT_TYPE	RW	0x0	Select offset binary (0x1) or 2's complement (0x0) data type. This sets the incoming data type and is required by the post processing modules for any data conversion. NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).
		[4]	FORMAT_ENABLE	RW	0x0	Enable data format conversion (see register bits above). NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).
		[3]	RESERVED	RO	0x0	Reserved for backward compatibility.
		[2]	RESERVED	RO	0x0	Reserved for backward compatibility.
		[1]	ADC_PN_TYPE_OWR	RW	0x0	If set, forces ADC_PN_SEL to 0x1, modified pn23 If both ADC_PN_TYPE_OWR and ADC_PN_SEL_OWR are set, they are ignored
		[0]	ENABLE	RW	0x0	If set, enables channel. A 0x0 to 0x1 transition transfers all the control signals to the respective channel processing module. If a channel is part of a complex signal (I/Q), even channel is the master and the odd channel is the slave. Though a single control is used, both must be individually selected.
0x0101	0x0404	REG_CHAN_STATUS				ADC Interface Control & Status
		[12]	CRC_ERR	RW1C	0x0	CRC errors. If set, indicates CRC error. Software must first clear this bit before initiating a transfer and monitor afterwards.
		[11:4]	STATUS_HEADER	RO	0x00	The status header sent by the ADC.(compatible with AD7768/AD7768-4/AD777x).
		[2]	PN_ERR	RW1C	0x0	PN errors. If set, indicates spurious mismatches in sync state. This bit is cleared if OOS is set and is only indicates errors when OOS is cleared.
		[1]	PN_OOS	RW1C	0x0	PN Out Of Sync. If set, indicates an OOS status. OOS is set, if 64 consecutive patterns mismatch from the expected pattern. It is cleared, when 16 consecutive patterns match the expected pattern.
		[0]	OVER_RANGE	RW1C	0x0	If set, indicates over range. Note that over range is independent of the data path, it indicates an over range over a data transfer period. Software must first clear this bit before initiating a transfer and monitor afterwards.
0x0102	0x0408	REG_CHAN_RAW_DATA				ADC Raw Data Reading
		[31:0]	ADC_READ_DATA[31:0]	RO	0x0000	Raw data read from the ADC.
0x0104	0x0410	REG_CHAN_CNTRL_1				ADC Interface Control & Status
		[31:16]	DCFILT_OFFSET[15:0]	RW	0x0000	DC removal (if equipped) offset. This is a 2's complement number added to the incoming data to remove a known DC offset. NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).
		[15:0]	DCFILT_COEFF[15:0]	RW	0x0000	DC removal filter (if equipped) coefficient. The format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).
0x0105	0x0414	REG_CHAN_CNTRL_2				ADC Interface Control & Status
		[31:16]	IQCOR_COEFF_1[15:0]	RW	0x0000	IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used, this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits). If SCALECORRECTION_ONLY is set, this implements the scale value correction for the current channel with the format 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
		[15:0]	IQCOR_COEFF_2[15:0]	RW	0x0000	IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value and the format is 2's complement. If matrix multiplication is used, this is the channel Q coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
0x0106	0x0418	REG_CHAN_CNTRL_3				ADC Interface Control & Status
		[19:16]	ADC_PN_SEL[3:0]	RW	0x0	Selects the PN monitor sequence type (available only if ADC supports it). - 0x0: pn9a (device specific, modified pn9) - 0x1: pn23a (device specific, modified pn23) - 0x4: pn7 (standard O.150) - 0x5: pn15 (standard O.150) - 0x6: pn23 (standard O.150) - 0x7: pn31 (standard O.150) - 0x9: pnX (device specific, e.g. ad9361) - 0x0A: Nibble ramp (Device specific e.g. adrv9001) - 0x0B: 16 bit ramp (Device specific e.g. adrv9001)
		[3:0]	ADC_DATA_SEL[3:0]	RW	0x0	Selects the data source to DMA. 0x0: input data (ADC) 0x1: loopback data (DAC)
0x0108	0x0420	REG_CHAN_USR_CNTRL_1				ADC Interface Control & Status
		[25]	USR_DATATYPE_BE	RO	0x0	The user data type format- if set, indicates big endian (default is little endian). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		[24]	USR_DATATYPE_SIGNED	RO	0x0	The user data type format- if set, indicates signed (2's complement) data (default is unsigned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		[23:16]	USR_DATATYPE_SHIFT[7:0]	RO	0x00	The user data type format- the amount of right shift for actual samples within the total number of bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		[15:8]	USR_DATATYPE_TOTAL_BITS[7:0]	RO	0x00	The user data type format- number of total bits used for a sample. The total number of bits must be an integer multiple of 8 (byte aligned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		[7:0]	USR_DATATYPE_BITS[7:0]	RO	0x00	The user data type format- number of bits in a sample. This indicates the actual sample data bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
0x0109	0x0424	REG_CHAN_USR_CNTRL_2				ADC Interface Control & Status
		[31:16]	USR_DECIMATION_M[15:0]	RW	0x0000	This holds the user decimation M value of the channel that is currently being selected on the multiplexer above. The total decimation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		[15:0]	USR_DECIMATION_N[15:0]	RW	0x0000	This holds the user decimation N value of the channel that is currently being selected on the multiplexer above. The total decimation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
0x0110	0x0440	REG_*				Channel 1, similar to register 0x100 to 0x10f.
0x0120	0x0480	REG_*				Channel 2, similar to register 0x100 to 0x10f.
0x01F0	0x07c0	REG_*				Channel 15, similar to register 0x100 to 0x10f.
Tue Mar 14 10:17:59 2023

DAC Common (axi_ad)

Click to expand regmap

0x0010	0x0040	REG_RSTN				DAC Interface Control & Status
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[2]	CE_N	RW	0x0	Clock enable, default is enabled(0x0). An inverse version of the signal is exported out of the module to control clock enables
		[1]	MMCM_RSTN	RW	0x0	MMCM reset only (required for DRP access). Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
		[0]	RSTN	RW	0x0	Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.
0x0011	0x0044	REG_CNTRL_1				DAC Interface Control & Status
		[0]	SYNC	RW	0x0	Setting this bit synchronizes channels within a DAC, and across multiple instances. This bit self clears.
		[1]	EXT_SYNC_ARM	RW	0x0	Setting this bit will arm the trigger mechanism sensitive to an external sync signal. Once the external sync signal goes high it synchronizes channels within a DAC, and across multiple instances. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.
		[2]	EXT_SYNC_DISARM	RW	0x0	Setting this bit will disarm the trigger mechanism sensitive to an external sync signal. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.
		[8]	MANUAL_SYNC_REQUEST	RW	0x0	Setting this bit will issue an external sync event if it is hooked up inside the fabric. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.
0x0012	0x0048	REG_CNTRL_2				DAC Interface Control & Status
		[16]	SDR_DDR_N	RW	0x0	Interface type (1 represents SDR, 0 represents DDR)
		[15]	SYMB_OP	RW	0x0	Select data symbol format mode (0x1)
		[14]	SYMB_8_16B	RW	0x0	Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b)
		[12:8]	NUM_LANES[4:0]	RW	0x0	Number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane)
		[7]	PAR_TYPE	RW	0x0	Select parity even (0x0) or odd (0x1).
		[6]	PAR_ENB	RW	0x0	Select parity (0x1) or frame (0x0) mode.
		[5]	R1_MODE	RW	0x0	Select number of RF channels 1 (0x1) or 2 (0x0).
		[4]	DATA_FORMAT	RW	0x0	Select data format 2's complement (0x0) or offset binary (0x1). NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
		[3:0]	RESERVED[3:0]	NA	0x00	Reserved
0x0013	0x004c	REG_RATECNTRL				DAC Interface Control & Status
		[7:0]	RATE[7:0]	RW	0x00	The effective dac rate (the maximum possible rate is dependent on the interface clock). The samples are generated at 1/RATE of the interface clock.
0x0014	0x0050	REG_FRAME				DAC Interface Control & Status
		[0]	FRAME	RW	0x0	The use of frame is device specific. Usually setting this bit to 1 generates a FRAME (1 DCI clock period) pulse on the interface. This bit self clears.
0x0015	0x0054	REG_STATUS1				DAC Interface Control & Status
		[31:0]	CLK_FREQ[31:0]	RO	0x00000000	Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock.
0x0016	0x0058	REG_STATUS2				DAC Interface Control & Status
		[31:0]	CLK_RATIO[31:0]	RO	0x00000000	Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).
0x0017	0x005c	REG_STATUS3				DAC Interface Control & Status
		[0]	STATUS	RO	0x0	Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores.
0x0018	0x0060	REG_DAC_CLKSEL				DAC Interface Control & Status
		[0]	DAC_CLKSEL	RW	0x0	Allows changing of the clock polarity. Note: its default value is CLK_EDGE_SEL
0x001A	0x0068	REG_SYNC_STATUS				DAC Synchronization Status register
		[0]	DAC_SYNC_STATUS	RO	0x0	DAC synchronization status. Will be set to 1 while waiting for the external synchronization signal This bit has an effect only the EXT_SYNC synthesis parameter is set.
0x001C	0x0070	REG_DRP_CNTRL				DRP Control & Status
		[28]	DRP_RWN	RW	0x0	DRP read (0x1) or write (0x0) select (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
		[27:16]	DRP_ADDRESS[11:0]	RW	0x00	DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
		[15:0]	RESERVED[15:0]	RO	0x0000	Reserved for backwards compatibility
0x001D	0x0074	REG_DRP_STATUS				DAC Interface Control & Status
		[17]	DRP_LOCKED	RO	0x0	If set indicates the MMCM/PLL is locked
		[16]	DRP_STATUS	RO	0x0	If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
		[15:0]	RESERVED[15:0]	RO	0x0000	Reserved for backwards compatibility
0x001E	0x0078	REG_DRP_WDATA				DAC Interface Control & Status
		[15:0]	DRP_WDATA[15:0]	RW	0x0000	DRP write data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
0x001F	0x007c	REG_DRP_RDATA				DAC Interface Control & Status
		[15:0]	DRP_RDATA	RO	0x0000	DRP read data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).
0x0020	0x0080	REG_DAC_CUSTOM_RD				DAC Read Configuration Data
		[31:0]	DAC_CUSTOM_RD[31:0]	RO	0x00000000	Custom Read of the available registers.
0x0021	0x0084	REG_DAC_CUSTOM_WR				DAC Write Configuration Data
		[31:0]	DAC_CUSTOM_WR[31:0]	RW	0x00000000	Custom Write of the available registers.
0x0022	0x0088	REG_UI_STATUS				User Interface Status
		[4]	IF_BUSY	RO	0x0	Interface busy. If set, indicates that the data interface is busy.
		[1]	UI_OVF	RW1C	0x0	User Interface overflow. If set, indicates an overflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.
		[0]	UI_UNF	RW1C	0x0	User Interface underflow. If set, indicates an underflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.
0x0023	0x008c	REG_DAC_CUSTOM_CTRL				DAC Control Configuration Data
		[31:0]	DAC_CUSTOM_CTRL[31:0]	RW	0x00000000	Custom Control of the available registers.
0x0028	0x00a0	REG_USR_CNTRL_1				DAC User Control & Status
		[7:0]	USR_CHANMAX[7:0]	RW	0x00	This indicates the maximum number of inputs for the channel data multiplexers. User may add different processing modules as inputs to the dac. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
0x002E	0x00b8	REG_DAC_GPIO_IN				DAC GPIO inputs
		[31:0]	DAC_GPIO_IN[31:0]	RO	0x00000000	This reads auxiliary GPI pins of the DAC core
0x002F	0x00bc	REG_DAC_GPIO_OUT				DAC GPIO outputs
		[31:0]	DAC_GPIO_OUT[31:0]	RW	0x00000000	This controls auxiliary GPO pins of the DAC core NOT-APPLICABLE if GPIO_DISABLE is set (0x1).
Tue Mar 14 10:17:59 2023

DAC Channel (axi_ad*)

Click to expand regmap

0x0100	0x0400	REG_CHAN_CNTRL_1				DAC Channel Control & Status (channel - 0)
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[21:16]	DDS_PHASE_DW[5:0]	R	0x0000	The DDS phase data width offers the HDL parameter configuration with the same name. This information is used in conjunction with REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10. More info at https://wiki.analog.com/resources/fpga/docs/dds
		[15:0]	DDS_SCALE_1[15:0]	RW	0x0000	The DDS scale for tone 1. Sets the amplitude of the tone. The format is 1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on 16-bits, note that if you do use both channels and set both scale to 0x4000, it is over-range. The final output is (tone_1_fullscale * scale_1) (tone_2_fullscale * scale_2). NOT-APPLICABLE if DDS_DISABLE is set (0x1).
0x0101	0x0404	REG_CHAN_CNTRL_2				DAC Channel Control & Status (channel - 0)
		[31:16]	DDS_INIT_1[15:0]	RW	0x0000	The DDS phase initialization for tone 1. Sets the initial phase offset of the tone. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
		[15:0]	DDS_INCR_1[15:0]	RW	0x0000	Sets the frequency of the phase accumulator. Its value can be calculated by ; where f_out is the generated output frequency, and f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. If DDS_PHASE_DW is greater than 16(from REG_CHAN_CNTRL_1), the phase increment for tone 1 is extended in REG_CHAN_CNTRL_9. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
0x0102	0x0408	REG_CHAN_CNTRL_3				DAC Channel Control & Status (channel - 0)
		[15:0]	DDS_SCALE_2[15:0]	RW	0x0000	The DDS scale for tone 2. Sets the amplitude of the tone. The format is 1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on 16-bits, note that if you do use both channels and set both scale to 0x4000, it is over-range. The final output is (tone_1_fullscale * scale_1) + (tone_2_fullscale * scale_2). NOT-APPLICABLE if DDS_DISABLE is set (0x1).
0x0103	0x040c	REG_CHAN_CNTRL_4				DAC Channel Control & Status (channel - 0)
		[31:16]	DDS_INIT_2[15:0]	RW	0x0000	The DDS phase initialization for tone 2. Sets the initial phase offset of the tone. If DDS_PHASE_DW is greater than 16(from REG_CHAN_CNTRL_1), the phase init for tone 2 is extended in REG_CHAN_CNTRL_10. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
		[15:0]	DDS_INCR_2[15:0]	RW	0x0000	Sets the frequency of the phase accumulator. Its value can be calculated by ; where f_out is the generated output frequency, and f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. If DDS_PHASE_DW is greater than 16(from REG_CHAN_CNTRL_1), the phase increment for tone 2 is extended in REG_CHAN_CNTRL_10. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
0x0104	0x0410	REG_CHAN_CNTRL_5				DAC Channel Control & Status (channel - 0)
		[31:16]	DDS_PATT_2[15:0]	RW	0x0000	The DDS data pattern for this channel.
		[15:0]	DDS_PATT_1[15:0]	RW	0x0000	The DDS data pattern for this channel.
0x0105	0x0414	REG_CHAN_CNTRL_6				DAC Channel Control & Status (channel - 0)
		[2]	IQCOR_ENB	RW	0x0	if set, enables IQ correction. NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).
		[1]	DAC_LB_OWR	RW	0x0	If set, forces DAC_DDS_SEL to 0x8, loopback If DAC_LB_OWR and DAC_PN_OWR are both set, they are ignored
		[0]	DAC_PN_OWR	RW	0x0	IF set, forces DAC_DDS_SEL to 0x09, device specific pnX If DAC_LB_OWR and DAC_PN_OWR are both set, they are ignored
0x0106	0x0418	REG_CHAN_CNTRL_7				DAC Channel Control & Status (channel - 0)
		[3:0]	DAC_DDS_SEL[3:0]	RW	0x00	Select internal data sources (available only if the DAC supports it). - 0x00: internal tone (DDS) - 0x01: pattern (SED) - 0x02: input data (DMA) - 0x03: 0x00 - 0x04: inverted pn7 - 0x05: inverted pn15 - 0x06: pn7 (standard O.150) - 0x07: pn15 (standard O.150) - 0x08: loopback data (ADC) - 0x09: pnX (Device specific e.g. ad9361) - 0x0A: Nibble ramp (Device specific e.g. adrv9001) - 0x0B: 16 bit ramp (Device specific e.g. adrv9001)
0x0107	0x041c	REG_CHAN_CNTRL_8				DAC Channel Control & Status (channel - 0)
		[31:16]	IQCOR_COEFF_1[15:0]	RW	0x0000	IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used, this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
		[15:0]	IQCOR_COEFF_2[15:0]	RW	0x0000	IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value and the format is 2's complement. If matrix multiplication is used, this is the channel Q coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).
0x0108	0x0420	REG_USR_CNTRL_3				DAC Channel Control & Status (channel - 0)
		[25]	USR_DATATYPE_BE	RW	0x0	The user data type format- if set, indicates big endian (default is little endian). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		[24]	USR_DATATYPE_SIGNED	RW	0x0	The user data type format- if set, indicates signed (2's complement) data (default is unsigned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		[23:16]	USR_DATATYPE_SHIFT[7:0]	RW	0x00	The user data type format- the amount of right shift for actual samples within the total number of bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		[15:8]	USR_DATATYPE_TOTAL_BITS[7:0]	RW	0x00	The user data type format- number of total bits used for a sample. The total number of bits must be an integer multiple of 8 (byte aligned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		[7:0]	USR_DATATYPE_BITS[7:0]	RW	0x00	The user data type format- number of bits in a sample. This indicates the actual sample data bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
0x0109	0x0424	REG_USR_CNTRL_4				DAC Channel Control & Status (channel - 0)
		[31:16]	USR_INTERPOLATION_M[15:0]	RW	0x0000	This holds the user interpolation M value of the channel that is currently being selected on the multiplexer above. The total interpolation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
		[15:0]	USR_INTERPOLATION_N[15:0]	RW	0x0000	This holds the user interpolation N value of the channel that is currently being selected on the multiplexer above. The total interpolation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).
0x010A	0x0428	REG_USR_CNTRL_5				DAC Channel Control & Status (channel - 0)
		[0]	DAC_IQ_MODE[0]	RW	0x0	Enable complex mode. In this mode the driven data to the DAC must be a sequence of I and Q sample pairs.
		[1]	DAC_IQ_SWAP[1]	RW	0x0	Allows IQ swapping in complex mode. Only takes effect if complex mode is enabled.
0x010B	0x042c	REG_CHAN_CNTRL_9				DAC Channel Control & Status (channel - 0)
		[31:16]	DDS_INIT_1_EXTENDED[15:0]	RW	0x0000	The extended DDS phase initialization for tone 1. Sets the initial phase offset of the tone. The extended init(phase) value should be calculated according to DDS_PHASE_DW value from REG_CHAN_CNTRL_1 NOT-APPLICABLE if DDS_DISABLE is set (0x1).
		[15:0]	DDS_INCR_1_EXTENDED[15:0]	RW	0x0000	Sets the frequency of tone 1's phase accumulator. Its value can be calculated by ; Where f_out is the generated output frequency, DDS_PHASE_DW value can be found in REG_CHAN_CNTRL_1 in case DDS_PHASE_DW is not 16, f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
0x010C	0x0430	REG_CHAN_CNTRL_10				DAC Channel Control & Status (channel - 0)
		[31:16]	DDS_INIT_2_EXTENDED[15:0]	RW	0x0000	The extended DDS phase initialization for tone 2. Sets the initial phase offset of the tone. The extended init(phase) value should be calculated according to DDS_PHASE_DW value from REG_CHAN_CNTRL_2 NOT-APPLICABLE if DDS_DISABLE is set (0x1).
		[15:0]	DDS_INCR_2_EXTENDED[15:0]	RW	0x0000	Sets the frequency of tone 2's phase accumulator. Its value can be calculated by ; Where f_out is the generated output frequency, DDS_PHASE_DW value can be found in REG_CHAN_CNTRL_2 in case DDS_PHASE_DW is not 16, f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. NOT-APPLICABLE if DDS_DISABLE is set (0x1).
0x0110	0x0440	REG_*				Channel 1, similar to registers 0x100 to 0x10f.
0x0120	0x0480	REG_*				Channel 2, similar to registers 0x100 to 0x10f.
0x01F0	0x07c0	REG_*				Channel 15, similar to registers 0x100 to 0x10f.
Fri Sep 8 16:01:53 2023

JESD TPL (up_tpl_common)

Click to expand regmap

0x00080	0x0200	REG_TPL_CNTRL				JESD, TPL Control
Address		Bits	Name	Type	Default	Description
DWORD	BYTE	Bits	Name	Type	Default	Description
		[3:0]	PROFILE_SEL	RW	0x00	Selects one of the available deframer/framers from the transport layer. Valid only if `PROFILE_NUM` > 1.
0x00081	0x0204	REG_TPL_STATUS				JESD, TPL Status
		[3:0]	PROFILE_NUM	RO	0x00	Number of supported framer/deframer profiles.
0x00090	0x0240	REG_TPL_DESCRIPTOR_1				JESD, TPL descriptor for profile
		[31:24]	JESD_F	RO	0x00	Octets per Frame per Lane.
		[23:16]	JESD_S	RO	0x00	Samples per Converter per Frame.
		[15:8]	JESD_L	RO	0x00	Lane Count.
		[7:0]	JESD_M	RO	0x00	Converter Count.
0x00091	0x0244	REG_TPL_DESCRIPTOR_2				JESD, TPL descriptor for profile
		[7:0]	JESD_N	RO	0x00	Converter Resolution.
		[15:8]	JESD_NP	RO	0x00	Total Number of Bits per Sample.
0x00092	0x0248	REG_*				Profile 1, similar to registers 0x00010 to 0x00011.
0x00094	0x0250	REG_*				Profile 2, similar to registers 0x00010 to 0x00011.
Tue Mar 14 10:17:59 2023

Design Guidelines

TBD

Software Guidelines

The software for this IP can be found as part of the FMCOMMS2/3/4/5 Reference Design at No-Os Software.
Linux is supported also using ADI Linux repository

References

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Wiki

Analog Devices Wiki

Table of Contents

AXI_AD9371

Features

Block Diagram

Functional Description

Interface Description

Parameters

I/O interface and signals

Register Map

Register Map base addresses for axi_ad9371

Base (common to all cores)

ADC Common (axi_ad*)

ADAQ8092

AD4858

AD7606X_PI

ADC Channel (axi_ad*)

DAC Common (axi_ad)

DAC Channel (axi_ad*)

JESD TPL (up_tpl_common)

Design Guidelines

Software Guidelines

References

Analog Devices Wiki

Table of Contents

AXI_AD9371

Features

Block Diagram

Functional Description

Interface Description

Parameters

I/O interface and signals

Register Map

Register Map base addresses for axi_ad9371

Base (common to all cores)

ADC Common (axi_ad*)

ADAQ8092

AD4858

AD7606X_PI

ADC Channel (axi_ad*)

DAC Common (axi_ad)

DAC Channel (axi_ad*)

JESD TPL (up_tpl_common)

Design Guidelines

Software Guidelines

References

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