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ADRV9026 HDL reference design

The reference design supports the following evaluation board:

Supported Carriers

Building the HDL project

General build instructions can be found here: Building HDL

Block Diagram

The data path and clock domains are depicted on the below diagram:

The Rx links (ADC Path) operate with the following parameters:

  • Rx Deframer parameters: L=4, M=4, F=4, S=1, N’=16, N = 16
  • Sample Rate : 250 MSPS
  • RX_DEVICE_CLK – 250 MHz (Lane Rate/40)
  • REF_CLK – 250MHz (Lane Rate/40)
  • JESD204B Lane Rate – 10Gbps
  • CPLL

The Tx links (DAC Path) operate with the following parameters:

  • Tx Framer parameters: L=4, M=4, F=4, S=1, N’=16, N = 16
  • Sample Rate : 250 MSPS
  • TX_DEVICE_CLK – 250 MHz (Lane Rate/40)
  • REF_CLK – 250MHz (Lane Rate/40)
  • JESD204B Lane Rate – 10Gbps
  • QPLL0

Clock sources

The clock sources are depicted on the below diagram:

More Information

Support

Analog Devices will provide limited online support for anyone using the core with Analog Devices components (ADC, DAC, Video, Audio, etc) via the EngineerZone.

/srv/wiki.analog.com/data/pages/resources/eval/user-guides/adrv9026/ad9026_hdl.txt · Last modified: 13 Feb 2024 14:44 by George Mois