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The reference design supports the following evaluation board:
General build instructions can be found here: Building HDL
The data path and clock domains are depicted on the below diagram:
The Rx links (ADC Path) operate with the following parameters:
The Tx links (DAC Path) operate with the following parameters:
The clock sources are depicted on the below diagram:
Analog Devices will provide limited online support for anyone using the core with Analog Devices components (ADC, DAC, Video, Audio, etc) via the EngineerZone.