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This version (17 May 2022 12:57) was approved by Liviu-Mihai Iacob.The Previously approved version (17 May 2022 12:45) is available.Diff

AD9695 FMC Card Reference Design

Overview

The AD9695 is a dual 14-bit, 1300/625MSPS analog-to-digital converter (ADC) featuring an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges.

The AD9695-FMC reference design is a processor based (e.g. Microblaze) embedded system. The design consists of a receive chain that transports the captured samples from the ADC to the system memory (DDR).

All cores from the receive chain are programmable through an AXI-Lite interface.

Supported Devices

Supported Carriers

Clock Selection

Synchrona Output Configuration

Only the channels presented in the clocking selection are relevant. For the rest, you can either disable them or just put a divided frequency of the source clock.

Block Diagram

The data path and clock domains are depicted on the below diagram:

The design has one JESD receive chain with 4 lanes at rate of 13Gbps. The JESD receive chain consists of a physical layer represented by an XCVR module, a link layer represented by an RX JESD LINK module and transport layer represented by a RX JESD TPL module. The link operates in Subclass 1.

The link is set for full bandwidth mode and operate with the following parameters:

Deframer paramaters: L=4, M=2, F=1, S=1, N’=16

SYSREF - 5.078125 MHZ
REFCLK – 325MHz (Lane Rate/40)
DEVICECLK -325 MHz
ADCCLK – 1300MHz
JESD204B Lane Rate – 13Gbps

The transport layer component presents on its output 128 bits at once on every clock cycle, representing 4 samples per converter. The two receive chains are merged together and transferred to the DDR with a single DMA.

Building the HDL project

ADI does not distribute the bit/elf files of these projects so they must be built from the sources available here. To get the source you must clone the HDL repository. Then go to the /projects/ad9695_fmc/zcu102 location and run the make command by typing in your command prompt:

Linux/Cygwin

user@analog:~$ cd hdl/projects/ad9695_fmc/zcu102
user@analog:~/hdl/projects/ad9695_fmc/zcu102$ make

A more comprehensive build guide can be found in the HDL User Guide.

System setup

Connections

AD9695 connected to ZCU102 on FMC HPC1

ZCU102 SYNCRONA
J79 CH9_P
J80 CH9_N
ADC9695 EVAL SYNCRONA
J202 CH10_P
J200 CH13
P202 CH14

ad9695_fmc_zcu102_setup_01.jpg

More Information

Support

Analog Devices will provide limited online support for anyone using the reference design with Analog Devices components via the EngineerZone.

resources/eval/user-guides/ad9695_fmc.txt · Last modified: 17 May 2022 12:57 by Liviu-Mihai Iacob