This version (06 Mar 2024 16:00) was approved by Andrei Dragomir.
AD9213-EVB HDL reference design
The reference design supports the following evaluation board:
| Hardware | Evaluation Document |
|---|---|
| AD9213 | AD9213 |
Supported Carriers
- VCU118 FMC+ Slot
Building the HDL project
General build instructions can be found here: Building HDL
Block Diagram
The data path and clock domains are depicted on the below diagram:
The design has one JESD receive chain having 16 lanes at rate of 12.5Gbps. The JESD receive chain consists of a physical layer represented by an XCVR module, a link layer represented by an RX JESD LINK module. The transport layer is common and is represented by a RX JESD TPL module. The link operates in Subclass 1 by using the SYSREF signal to edge align the internal local multiframe clock and to release the received data in the same moment from all lanes, therefore ensuring that data from all channels is synchronized at the application layer.
The link is set for full bandwidth mode and operates with the following parameters:
- Deframer paramaters: L=16, M=1, F=2, S=16, N’=16, N=16
- GLBLCLK – 312.5MHz (Lane Rate/40)
- REFCLK – 625 MHz (Lane Rate/20)
- SYSREF – 19.53MHz (DEVCLK/512)
- DEVCLK – 10000MHz
- JESD204B Lane Rate – 12.5Gbps
Clock sources
The clock sources are depicted on the below diagram:
More Information
Support
Analog Devices will provide limited online support for anyone using the core with Analog Devices components (ADC, DAC, Video, Audio, etc) via the EngineerZone.
resources/eval/user-guides/ad9213_evb/ad9213_evb_hdl.txt · Last modified: 26 Jun 2023 13:06 by Andrei Dragomir