The HDL reference design for the EVAL-AD4630_FMCZ and EVAL-AD4030_FMCZ provides all the interfaces that are necessary to interact with the device using a Xilinx FPGA development board.
The design has all the necessary infrastructure to acquire data from the AD4630-24 24-bit dual-channel precision SAR ADC, AD4630-16 16-bit dual channel precision SAR ADC and AD4030-24 single channel ADC, supporting continuous data capture at maximum 2 MSPS data rate. The design targeted to the Zedboard, which is a low cost FPGA carrier board from Digilent, using a Zynq-7000 re-programmable SoC from Xilinx.
The design is built upon ADI's generic HDL reference design framework. More information about the framework can be found in the ADI Reference Designs HDL User Guide wiki page.
The reference design uses the SPI Engine Framework to interface with the AD4630 ADC.
The design supports almost all possible digital interface configurations of the device. In echo clock mode, because the clock for data latching is routed back through the BUSY line, an additional data capture module is used for saving the received samples and transmitting forward for the DMA.
There are three modes in which the system can run. Refer to the AD4630-24, AD4630-16 or AD4030-24 data sheet section titled SAMPLE CONVERSION TIMING AND DATA TRANSFER for more explanation of data transfer zones.
The main aspect of this mode is the fact that it is using the BUSY signal from the ADC to trigger the Offload module.
Data is then clocked out by the Execution module and transferred to the DMA by the Offload module. CNV is always generated by the AXI PWM GEN IP core regardless of the mode.
Zone 1 transfer is not currently supported by the pre-compiled HDL files that are included in the SD card image that is provided with the evaluation board.
The following block diagram shows the simplified architecture of the design:
In this mode, the BUSY signal is not used and both the CNV and the Offload trigger signals are generated by the AXI PWM GEN core. The reason for using two PWM outputs instead of a common one is to accommodate for the averaging mode where the two signals will have different frequencies.
In this configuration, the ADC's BUSY-SCKOUT pin functions as a bit-clock output and is generated by looping-through the host’s SCK. The SPI engine is driving the SPI signals except it is no longer reading the data. For this purpose, the Data Capture IP is used. This also allows for reading data in DDR mode.
The design supports the following interface and clock modes both in SDR and DDR:
|1 Lane per channel||2 Lane per channel||4 Lane per channel|
|Echo Clock mode||yes||yes||yes|
In order to build the HDL design the user has to go through the following steps: