All the HDL sources can be found in the following git repository:
We assume that the user is familiar with git. Knows how to clone the repository, how to check its status or how to switch between branches.
If you want to pull down the sources as soon as possible, just do the following few steps:
The root of the HDL repository has the following structure:
. ├─ .github ├─ docs ├─ projects ├─ library ├─ .gitattributes ├─ .gitignore ├─ LICENSE ├─ Makefile └─ README.md
The repository is divided into two separate sections:
The file .gitattributes is used to properly handle different line endings. And the .gitignore specifies intentionally untracked files that Git should ignore. The root Makefile can be used to build all the project of the repository. To learn more about hdl Makefiles visit the Building & Generating programming files section.
. ├─ projects │ ├ ad6676evb │ ├ ad9467_fmc │ · │ ├ common │ ├ fmcomms2 │ │ ├ ac701 │ │ ├ common │ │ ├ kc705 │ │ · │ │ ├ zed │ │ └ Makefile │ ├ adrv9009 │ ├ scripts │ · │ └ Makefile └─ library · └─ README.md
Besides the project folders, there are two special folders inside the /hdl/projects:
Inside a project folder, you can find folders with an FPGA carrier name (e.g. ZC706) which in general contains all the carrier board specific files, and a folder called common which contains the project specific files. If you can not find your FPGA board name in a project folder, that means your FPGA board with that particular FMC board is not supported.
. ├─ projects ├─ library │ ├─ axi_ad6676 │ ├─ axi_ad9122 │ ├─ axi_ad9144 │ · │ ├─ common │ ├─ interfaces │ ├─ scripts │ ├─ util_pack │ · │ └ Makefile · └─ README.md
The library folder contains all the IP cores and common modules. An IP, in general, contains Verilog files, which describe the hardware logic, constraint files, to ease timing closure, and Tcl scripts, which generate all the other files required for IP integration (*_ip.tcl for Vivado and *_hw.tcl for Quartus) .
The repository may contain multiple branches and tags. The master branch is the development branch (latest sources, but not stable). If you check out this branch, some builds may fail. If you are not into any kind of experimentation, you should only check out one of the release branch.
All our release branches have the following naming convention: hdl_[year_of_release]_r[1 or 2]. (e.g. hdl_2014_r2)
ADI does two releases each year when all the projects get an update to support the latest tools and get additional new features. The master branch is always synchronized with the latest release. If you are in doubt, ask us on FPGA Engineer Zone.