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This user guide describes the AD9680/AD9234 evaluation board which provides all of the support circuitry required to operate the ADC in its various modes and configurations. Users wanting to evaluate the single channel AD9690 should utilize/evaluate Channel A on the AD9680-500EBZ, or AD9680-1000EBZ. The application software used to interface with the devices is also described. This user guide wiki applies to the following evaluation boards:
Evaluation Board Part Number | Description | Board Revision |
---|---|---|
AD9680-1250EBZ | Evaluation board for AD9680-1250; Full Bandwidth | 9680CE04B |
AD9680-1000EBZ | Evaluation board for AD9680-1000; Full Bandwidth | 9680CE04B |
AD9680-820EBZ | Evaluation board for AD9680-820; Full Bandwidth | 9680CE04B |
AD9680-500EBZ | Evaluation board for AD9680-500; Full Bandwidth | 9680CE04B |
AD9234-1000EBZ | Evaluation board for AD9234-1000; Full Bandwidth | 9680CE04B |
AD9234-500EBZ | Evaluation board for AD9234-500; Full Bandwidth | 9680CE04B |
AD9680-LF1000EBZ | Evaluation board for AD9680-1000; up to 1GHz Input Bandwidth | 9680CE02B |
AD9680-LF820EBZ | Evaluation board for AD9680-820; up to 1GHz Input Bandwidth | 9680CE02B |
AD9680-LF500EBZ | Evaluation board for AD9680-500; up to 1GHz Input Bandwidth | 9680CE02B |
AD9234-LF1000EBZ | Evaluation board for AD9234-1000; up to 1GHz Input Bandwidth | 9680CE02B |
AD9234-LF500EBZ | Evaluation board for AD9234-500; up to 1GHz Input Bandwidth | 9680CE02B |
The AD9680 and AD9234 data sheets provide additional information and should be consulted when using the evaluation board. All documents and software tools are available at www.analog.com/hsadcevalboard. For additional information or questions, send an email to highspeed.converters@analog.com.
Figure 3 below compares the bandwidth available on the AD9680/AD9234 normal evaluation boards and the “LF” boards
Figure 3. Comparison of Bandwidth on the Normal and the “LF” boards
The AD9680-1000EBZ/AD9234-1000EBZ can be evaluated using the ADS7-V2EBZ FPGA data capture boards. Figures 3 and 4 below show the AD9680-1000EBZ/AD9234-1000EBZ connected to the ADS7-V1EBZ and ADS7-V2EBZ respectively.
Figure 3. Evaluation Board Connection—AD9680-1000EBZ/AD9234-1000EBZ (on Left) and ADS7-V1EBZ (on Right)
Please note : ADS7-V1EBZ has been obsoleted and is NOT recommended for new evaluations.
Figure 4. Evaluation Board Connection—AD9680-LF1000EBZ/AD9234-LF1000EBZ (on Left) and ADS7-V2EBZ (on Right)
This section provides quick start procedures for using the evaluation board for AD9680 or AD9234.
Before using the software for testing, configure the evaluation board as follows:
Figure 4. Device Manager showing ADS7-V1EBZ
bps/lane, where
(Default Nprime = 16)
Figure 5. Selecting the AD9680 canvas
Figure 6. Programming the ADS7-V2EBZ
Figure 7. Expanding Display in VA
Figure 8. Changing the ADC Capture Settings
Figure 9. Setting the clock frequency and Capture length
==== SPIController Setup ==== - Click Start All Programs Analog Devices SPIController SPIController - Select the appropriate configuration file when prompted. - In the Global tab, under the Generic Read/Write section, write 0x81 to register 0x000. This issues a Soft reset for the DUT.
Figure 9. Sending a Soft Reset to the AD9680
===== Sample Configuration 1: Full Bandwidth Mode ===== - Set the ADC Configuration Registers in ADCBase0 tab. Write Chip Mode Control Register address 0x200 to Full Bandwidth Mode and Chip Decimation Ratio Control Register 0x201 to Full Sample Rate.
Figure 10. Setting Chip Mode Control and Decimation Ratio Registers
- For JESD204B setting, proceed to ADCBase3 tab. Check the Serial Transmit Power Down box in JESD204B Link Control Register (0x571).
Figure 11. JESD204B Serial Transmit Power Down
- Set the Lane Rate setting register 0x56E to Maximum Lane Rate. The decision to use Maximum Lane Rate mode or Low Lane Rate mode should be based on the Lane Line Rate that was calculated in Configuring the Board section.
Figure 12. Setting the JESD204B Lane Rate
- Set the JESD204B Quick Configuration register (0x570). For 1000MSPS operation with NO DDCs (Full Bandwidth Mode), the values for L.M.F are 4.2.1
Figure 13. Setting the JESD204B Quick Configuration Register
- Proceed to ADCBase4 tab and set/read the registers 0x58B, 0x58C, 0x58D, and 0x58E to check if the desired JESD204B configurations on ADCBase3 tab are reflected.
Figure 14. Reading the JESD204B Configuration Registers
- On address 0x58F, change the Converter Resolution to 14 for AD9680 (12 for AD9234). - Back to ADCBase3 tab, uncheck the Serial Transmit Power Down box in JESD204B Link Control Register (0x571). - After the quick configuration setting is completed, the PLL Lock Detect register 0x56F will read 0x80 to denote a lock. The SPIController interface will show a “1” to denote a lock.
Figure 15. Reading the PLL Status Register
- Individual Channel control for ADC A and ADC B are done using the Device Index Register (0x008) in the Global tab.
Figure 16. Device Index for ADC Channel A and Channel B
- Under ADC A and ADC B tabs the options for Channel A and B are listed. Default settings have been programmed to ensure optimal performance for the input bandwidth and sample rate. Only the following options need to be operated with: - Chip Configuration Register (0x002): This option allows the channel to be powered on - Buffer Current Setting (0x018): This option allows the buffer current to change to enable better harmonic performance at different frequencies. At high analog input frequencies, the buffer current may need to be increased to optimize harmonic distortion performance (HD2, HD3). Keep in mind that at high frequencies, the performance is also jitter limited. So increasing the buffer currents may lead to diminishing returns with higher power consumption. Refer to the datasheet to understand the relationship between IAVDD3 and Buffer Current Setting. - Analog Input Differential Termination (0x016): This sets the input termination. Recommended settings are 500, 200, 100, 50 ohms. At lower termination settings, the harmonic distortion performance may show improvement, but the analog input signal amplitude will be reduced. - Input Full Scale Range (0x025): At high input frequencies, in order to preserve the linearity of the input buffer, it may be beneficial to reduce the input full-scale range in order to get more harmonic distortion performance. This in turn may negatively affect the SNR of the ADC. ==== Obtaining an FFT ==== - Click the Run button in VisualAnalog , you should see the captured data similar to the plot shown in Figure 17.
Figure 17. AD9680-1000 FFT at 170MHz Analog Input
- Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the Fund Power reading in the left panel of the VisualAnalog FFT window.) - To save the FFT plot do the following - Click on the Float Form button in the FFT window
Figure 18. Floating the FFT window
- Click on File Save Form As button and save it to a location of choice
Figure 19. Saving the FFT
===== Sample Configuration 2: Two ADCs Plus Two DDCs, Decimate by 4 ===== ==== SPIController Setup ==== - Click Start All Programs Analog Devices SPIController SPIController - Select the appropriate configuration file when prompted. - In the VisualAnalog Setup, follow Steps 1-5 and after that, click the ADC Data Capture Settings, remove Ch.A and Ch.B output data, and add Ch. DDC0 and Ch. DDC1 output data.
Figure 20. VisualAnalog ADC Data Capture Settings for DDC
- In the Global tab, under the Generic Read/Write section, write 0x81 to register 0x000. This issues a Soft reset for the DUT.
Figure 21. Sending a Soft Reset to the AD9680
- Set the ADC Configuration Registers in ADCBase0 tab. Write Chip Mode Control Register (0x200) to Two Digital Down Converters and Chip Decimation Ratio Control Register (0x201) to Decimate by 4.
Figure 22. Setting Chip Mode Control and Decimation Ratio Registers
- For DDC settings, proceed to ADCBase1 tab and configure DDC0 and DDC1 Control Registers with corresponding addresses of 0x310 and 0x330, respectively, to Real Mixer, Variable IF Mode, Complex (I/Q) Decimate by 4. Channel Input Selection for address 0x311 is set to Channel A for I and Q while address 0x331 is set to Channel B for I and Q.
Figure 23. DDC Control Registers
- For frequency tuning word (FTW), addresses 0x314-315 are set as required by application for DDC0, and addresses 0x334-335 are set as required by application for DDC1. Figure xx below shows the calculation for NCO Frequency Tuning Word.
Figure 24. Frequency Tuning Word Formula
- After setting all DDC registers, go to Generic Write/Read in Global tab and write 0x10 to address 0x300 (DDC soft reset), and write back to 0x00 (DDC normal operation). Same process can be done by checking and unchecking the DDC Soft Reset box.
Figure 25. DDC Synchronization Control Register
- For JESD204B setting, proceed to ADCBase3 tab. Check the Serial Transmit Power Down box in JESD204B Link Control Register (0x571).
Figure 26. JESD204B Serial Transmit Power Down
- Set the Lane Rate setting register 0x56E to Maximum Lane Rate. The decision to use Maximum Lane Rate mode or Low Lane Rate mode should be based on the Lane Line Rate that was calculated in Configuring the Board section.
Figure 27. Setting the JESD204B Lane Rate
- Set the JESD204B Quick Configuration register (0x570). For 1000MSPS operation with 2 DDCs (Two Digital Down Converters), the values for L.M.F are 2.4.4.
Figure 28. Setting the JESD204B Quick Configuration Register
- Proceed to ADCBase4 tab and set/read the registers 0x58B, 0x58C, 0x58D, and 0x58E to check if the desired JESD204B configurations on ADCBase3 tab are reflected.
Figure 29. Reading the JESD204B Configuration Registers
- On address 0x58F, change the Converter Resolution to 14 for AD9680 (12 for AD9234). - Back to ADCBase3 tab, uncheck the Serial Transmit Power Down box in JESD204B Link Control Register (0x571). - After the quick configuration setting is completed, the PLL Lock Detect register 0x56F will read 0x80 to denote a lock. The SPIController interface will show a “1” to denote a lock.
Figure 30. Reading the PLL Status Register
- Individual Channel control for ADC A and ADC B are done using the Device Index Register (0x008) in the Global tab.
Figure 31. Device Index for ADC Channel A and Channel B
- Under ADC A and ADC B tabs the options for Channel A and B are listed. Default settings have been programmed to ensure optimal performance for the input bandwidth and sample rate. Only the following options need to be operated with: - Chip Configuration Register (0x002): This option allows the channel to be powered on - Buffer Current Setting (0x018): This option allows the buffer current to change to enable better harmonic performance at different frequencies. At high analog input frequencies, the buffer current may need to be increased to optimize harmonic distortion performance (HD2, HD3). Keep in mind that at high frequencies, the performance is also jitter limited. So increasing the buffer currents may lead to diminishing returns with higher power consumption. Refer to the datasheet to understand the relationship between IAVDD3 and Buffer Current Setting. - Analog Input Differential Termination (0x016): This sets the input termination. Recommended settings are 500, 200, 100, 50 ohms. At lower termination settings, the harmonic distortion performance may show improvement, but the analog input signal amplitude will be reduced. - Input Full Scale Range (0x025): At high input frequencies, in order to preserve the linearity of the input buffer, it may be beneficial to reduce the input full-scale range in order to get more harmonic distortion performance. This in turn may negatively affect the SNR of the ADC. ==== Obtaining an FFT ==== - Click the Run button in VisualAnalog , you should see the captured data similar to the plot shown in Figure 32.
Figure 32. AD9680-1000 FFT at 150.3MHz Analog Input, NCO_FTW = 155MHz
- Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the Fund Power reading in the left panel of the VisualAnalog FFT window.) ===== Validating Deterministic Latency Using Subclass 1 Operation ===== The following .zip files contain the files needed for users to validate subclass 1 operation and observe the latency differences between subclass 0 and subclass 1 operation. The “Validating Subclass 1 Operation of the AD9680” document will guide the user through the necessary steps to perform this validation. SPI Controller scripts for several full bandwidth modes are included for convenience. ad9680_ads7v2_dl_demo.zip spicontroller_scripts_for_dl_demo.zip ===== Troubleshooting Tips ===== FFT plot appears abnormal * If you see a normal noise floor when you disconnect the signal generator from the analog input, be sure you are not overdriving the ADC. Reduce input level if necessary. * In VisualAnalog, Click on the Settings button in the Input Formatter block. Check that Number Format is set to the correct encoding (twos compliment by default). Repeat for the other channel. * Issue a Data Path Soft Reset through SPIController Global tab as shown in Figure 33
Figure 33. Issuing a data path soft reset through SPIController
The FFT plot appears normal, but performance is poor. * Make sure you are using the appropriate band-pass filter on the analog input. * Make sure the signal generators for the clock and the analog input are clean (low phase noise). * If you are using non-coherent sampling, change the analog input frequency slightly, or use coherent frequencies. * Make sure the SPI config file matches the product being evaluated. The FFT window remains blank after the Run button is clicked * Make sure the evaluation board is securely connected to the ADS7-V2. * Make sure the FPGA has been programmed by verifying that the Config DONE LED is illuminated on the ADS7-V2. If this LED is not illuminated reprogram the FPGA through VisualAnalog. If the LED still does not illuminate disconnect the USB and power cord for 15 seconds. Connect again and repeat the ADS7-V2 setup process. * Make sure the correct FPGA bin file was used to program the FPGA. * Be sure that the correct sample rate is programmed. Click on the Settings button in the ADC Data Capture block in VisualAnalog, and verify that the Clock Frequency is properly set.
Figure 34. Setting the correct clock frequeency in VisualAnalog
* Ensure that the REFCLOCK is ON and set to the appropriate frequency. * Restart SPIController. VisualAnalog indicates that the “FIFO capture timed out” or “FIFO not ready for read back” * Make sure all power and USB connections are secure. * Make sure that the REFCLOCK is ON and set to the appropriate frequency. VisualAnalog displays a blank FFT when the RUN button is clicked * Ensure that the clock to the ADC is supplied. Using SPIController ADCBase0 tab the status of the clock can be read out. See figure 35.
Figure 35. Clock Detection Status Register
* Ensure that the ADC's PLL is locked by checking the status of the PLL lock detect register 0x56F. This can be done using SPIController.