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This version (10 Nov 2023 07:45) was approved by Janadrian Alipio.The Previously approved version (17 Nov 2022 03:13) is available.Diff

Table of Contents

EVALUATING THE AD9680/AD9690/AD9234 ANALOG-TO-DIGITAL CONVERTER

Preface

This user guide describes the AD9680/AD9234 evaluation board which provides all of the support circuitry required to operate the ADC in its various modes and configurations. Users wanting to evaluate the single channel AD9690 should utilize/evaluate Channel A on the AD9680-1250EBZ, or AD9680-1000EBZ. The application software used to interface with the devices is also described. This user guide wiki applies to the following evaluation boards:

Evaluation Board Part Number Description Board Revision
AD9680-1250EBZ Evaluation board for AD9680-1250; Full Bandwidth 9680CE04B
AD9680-1000EBZ Evaluation board for AD9680-1000; Full Bandwidth 9680CE04B
AD9680-820EBZ Evaluation board for AD9680-820; Full Bandwidth 9680CE04B
AD9680-500EBZ Evaluation board for AD9680-500; Full Bandwidth 9680CE04B
AD9234-1000EBZ Evaluation board for AD9234-1000; Full Bandwidth 9680CE04B
AD9234-500EBZ Evaluation board for AD9234-500; Full Bandwidth 9680CE04B
AD9680-LF1000EBZ Evaluation board for AD9680-1000; up to 1GHz Input Bandwidth 9680CE02B
AD9680-LF820EBZ Evaluation board for AD9680-820; up to 1GHz Input Bandwidth 9680CE02B
AD9680-LF500EBZ Evaluation board for AD9680-500; up to 1GHz Input Bandwidth 9680CE02B
AD9234-LF1000EBZ Evaluation board for AD9234-1000; up to 1GHz Input Bandwidth 9680CE02B
AD9234-LF500EBZ Evaluation board for AD9234-500; up to 1GHz Input Bandwidth 9680CE02B


The AD9680 and AD9234 data sheets provide additional information and should be consulted when using the evaluation board. All documents and software tools are available at www.analog.com/hsadcevalboard. For additional information or questions, send an email to highspeed.converters@analog.com.

AD9680/AD9234 Evaluation Board

Figure 1. AD9680/AD9234 Evaluation Board for full 2GHz Input Bandwidth

Figure 2. AD9680/AD9234 Low Frequency Evaluation Board up to 1GHz Input Bandwidth

Figure 3 below compares the bandwidth available on the AD9680/AD9234 normal evaluation boards and the “LF” boards.

Figure 3. Comparison of Bandwidth on the Normal and the “LF” boards

Typical Measurement Setup

The AD9680-1250EBZ/AD9234-1000EBZ can be evaluated using the ADS7-V2EBZ FPGA data capture boards. Figures 4 and 5 below show the AD9680-1250EBZ/AD9234-1000EBZ connected to the ADS7-V1EBZ and ADS7-V2EBZ respectively.

Figure 4. Evaluation Board Connection—AD9680-1250EBZ/AD9234-1000EBZ (on Left) and ADS7-V1EBZ (on Right)

Note: ADS7-V1EBZ has been obsoleted and is NOT recommended for new evaluations.

Figure 5. Evaluation Board Connection—AD9680-LF1000EBZ/AD9234-LF1000EBZ (on Left) and ADS7-V2EBZ (on Right)

Features

  • Full featured evaluation board for the AD9680 and AD9234. Includes:
    • AD9680-1250EBZ
    • AD9680-1000EBZ, AD9680-LF1000EBZ
    • AD9680-820EBZ, AD9680-LF820EBZ
    • AD9680-500EBZ, AD9680-LF500EBZ
    • AD9234-1000EBZ, AD9234-LF1000EBZ
    • AD9234-500EBZ, AD9234-LF500EBZ
  • SPI interface for setup and control
  • Wide band Balun driven input for the AD9680-1250EBZ, AD9680-1000EBZ, AD9680-820EBZ, AD9680-500EBZ, AD9234-1000EBZ and AD9234-500EBZ.
  • Double balun input for AD9680-LF1000EBZ, AD9680-LF820EBZ, AD9680-LF500EBZ, AD9234-LF1000EBZ and AD9234-LF500EBZ.
  • No external supply needed. Uses 12V-1A and 3.3V-3A supplies from FMC.
  • VisualAnalog® and SPI controller software interfaces.
  • ACE (Analysis | Control | Evaluation) software interface.
  • On-board Crystal oscillator for AD9680-LF1000EBZ, AD9680-LF820EBZ, AD9680-LF500EBZ, AD9234-LF1000EBZ, AD9234-LF500EBZ

Helpful Documents

Software Needed

Design and Integration Files

Equipment Needed

  • AD9680 or AD9234 Evaluation board
  • ADS7-V2EBZ FPGA-based data capture kit
  • 12V, 6.5A switching power supply (such as the SL POWER CENB1080A1251F01 supplied with ADS7-V2EBZ)
  • PC running Windows®
  • USB 2.0 High-speed A to B Cable
  • Low phase noise analog input source and antialiasing filter
  • Low phase noise sample clock source
  • Reference clock source

Getting Started

This section provides quick start procedures for using the evaluation board for AD9680 or AD9234.

Configuring the Board

Before using the software for testing, configure the evaluation board as follows:

  1. Connect the evaluation board to the ADS7-V2EBZ data capture board, as shown in Figure 5.
  2. Connect one 12V, 6.5A switching power supply (such as the CENB1080A1251F01 supplied) to P7 on the ADS7-V2EBZ board.
  3. Connect the Standard-B USB port of the ADS7-V2EBZ board to the PC with the supplied USB cable.
  4. Turn on the ADS7-V2EBZ.
  5. The ADS7-V2EBZ will appear in the Device Manager as shown in Figure 6.

    Figure 6. Device Manager showing ADS7-V1EBZ

  6. If the Device Manager does not show the ADS7-V2EBZ listed as shown in Figure 6, unplug all USB devices from the PC, uninstall and re-install ACE or SPIController and VisualAnalog and restart the hardware setup from step 1.
  7. On the ADC evaluation board, provide a clean, low jitter 1.25 GHz clock source to connector J801 and set the amplitude to 14dBm. This is the ADC Sample Clock.
  8. On the ADC evaluation board, provide a clean, low jitter clock source to connector J804 and set the amplitude to 10dBm. This is the Reference Clock for the gigabit transceivers in the FPGA. The REFCLK frequency can be calculated using the following empirical formulae:

    LaneLineRate=M*Nprime*(10/8)*f_{out}/Lbps/lane, where

    f_{out} = f_{ADC SAMPLE CLOCK}/DecimationRatio, Nprime=8 or 16(Default Nprime = 16)

    REFCLK = LaneLineRate/20

    Default Nprime = 16; DCM = Chip Decimation Ratio (DCM = 1 for Full Bandwidth Mode); M = Virtual Converters; L = Lanes

  9. On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel A to P200. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.)
  10. On the ADC evaluation board, use a clean signal generator with low phase noise to provide an input signal for channel B to P202. Use a shielded, RG-58, 50 Ω coaxial cable to connect the signal generator output to the ADC Evaluation Board. For best results, use a narrow-band, band-pass filter with 50 Ω terminations and an appropriate center frequency. (ADI uses TTE, Allen Avionics, and K & L band-pass filters.)

Software Setup

Note: ACE plugin is only available for AD9680 evaluation boards. Use VisualAnalog/SPIController for AD9690/AD9234 evaluation boards.

ACE Setup

ACE Setup

  1. Download and install ACE if it is not already installed.
  2. The AD9680 ACE plug-in can be found under the AD9680 Evaluation Board Software Section, or through ACE's Plug-In Manager (Tools → Manage Plug-Ins).
    Tip: Some browsers (Such as Internet Explorer) may save the file as a .zip file instead of an .acezip file. If this happens, simply download and rename the file with an .acezip file extension.
  3. Once the .acezip file has been downloaded from the Analog Devices website, right click on it and install the plug-in, or double click to install.
  4. Click Start → All Programs → Analog Devices → ACE → ACE
  5. The AD9680 plug-in should appear as in Figure 7 if installed correctly.

    Figure 7. ACE's AD9680 Plug-in

  6. If the AD9680 plug-in does not appear, or no board is detected, make sure the ADS7-V2 is powered on and the evaluation board is properly connected. Make sure that ACE has been updated to the most recent version and the necessary plug-ins have been installed.
    Note: Differences may occur between ACE plug-in versions, including the version number seen in Figure 7 above or components in any of the other images below - however, these will not affect the performance of the part, nor the fundamental features described in this user guide.
  7. Double click on the plug-in to open it. This will open the AD9680 Board View.

    Figure 8. AD9680 Board View

    Note: ACE will automatically program the FPGA (FPGA_DONE LED should be lit up) and load the default full bandwidth configuration.
  8. Double click on the blue AD9680 chip (in the middle of the board) to open up the Chip View.

    Figure 9. AD9680 Chip View

Visual Analog & SPI Controller Setup

Visual Analog & SPI Controller Setup

Visual Analog Setup

  1. Click Start right All Programs right Analog Devices right VisualAnalog right VisualAnalog
  2. On the VisualAnalog “New Canvas” window, click ADCrightDualrightAD9680 or ADCrightDualrightAD9234

    Figure 10. Selecting the AD9680 canvas

  3. At this point, VisualAnalog will automatically detect the evaluation board and the FPGA data capture board and ask if it can program the FPGA with the appropriate bin file. This is shown in figure 11. Programming the FPGA will provide power to the evaluation board.

    Figure 11. Programming the ADS7-V2EBZ

  4. If VisualAnalog opens with a collapsed view, click on the “Expand Display” icon (see figure 12)

    Figure 12. Expanding Display in VisualAnalog

  5. Click the Settings button in the ADC Data Capture block as shown in Figure 13

    Figure 13. Changing the ADC Capture Settings

  6. On the General tab make sure the clock frequency is set to the appropriate sample rate (eg. 1250 MHz or 1000 MHz). The FFT capture length may be changed to 131072 (128k) or 262144 (256k) per channel. The ADS7-V2 FPGA software supports up to 2M FFT capture (1M per channel)

    Figure 14. Setting the clock frequency and Capture length

  7. On the Device tab. Make sure that Enable Alternate REFCLK option is unchecked.

    Figure 15. Setting the clock frequency and capture length

  8. Click OK

SPI Controller Setup

  1. Click Start right All Programs right Analog Devices right SPIController right SPIController
  2. Select the appropriate configuration file when prompted.
  3. In the Global tab, under the Generic Read/Write section, write 0x81 to register 0x000. This issues a Soft Reset for the DUT or just click Reset at CHIP PORT CFG(0).

    Figure 16. Sending a Soft Reset to the AD9680

  4. Individual Channel control for ADC A and ADC B are done using the Device Index Register (0x008) in the Global tab.

    Figure 17. Device Index for ADC Channel A and Channel B

  5. Under ADC A and ADC B tabs the options for Channel A and B are listed. Default settings have been programmed to ensure optimal performance for the input bandwidth and sample rate. Only the following options need to be operated with:
    1. Chip Configuration Register (0x002): This option allows the channel to be powered on.
    2. Buffer Current Setting (0x018): This option allows the buffer current to change to enable better harmonic performance at different frequencies. At high analog input frequencies, the buffer current may need to be increased to optimize harmonic distortion performance (HD2, HD3). Keep in mind that at high frequencies, the performance is also jitter limited. So increasing the buffer currents may lead to diminishing returns with higher power consumption. Refer to the datasheet to understand the relationship between IAVDD3 and Buffer Current Setting.
    3. Analog Input Differential Termination (0x016): This sets the input termination. Recommended settings are 500, 200, 100, 50 ohms. At lower termination settings, the harmonic distortion performance may show improvement, but the analog input signal amplitude will be reduced.
    4. Input Full Scale Range (0x025): At high input frequencies, in order to preserve the linearity of the input buffer, it may be beneficial to reduce the input full-scale range in order to get more harmonic distortion performance. This in turn may negatively affect the SNR of the ADC.

      Figure 18. SPI Controller Channel A and B Options

Sample Configuration 1: Full Bandwidth Mode

ACE Configuration

ACE Configuration

  1. Under Initial Configuration at board view, set the clock input to 1250 MHz. Change the Clock Divide Ratio to divide by 1. Change the Chip Operation Mode to full bandwidth mode. Change the number of Lane to 4. Change the number of Virtual Converter to 2. Change the number of Octets per Frame to 1. Click Apply to apply the chip settings. Set the reference clock to 625 MHz to match these settings.

    Figure 19. Chip Settings

    Note: ACE will automatically load the default full bandwidth configuration and can skip to step 7 to proceed to Analysis tab to capture data.
  2. The chip view will update to reflect the changes made to the board. If any changes are made, the chip can be read by clicking the Read All button.

    Figure 20. Read All Button

  3. Set the PLL Control serial lane rate to 6.25 Gbps to 12.5 Gbps and click Apply Changes. The decision to use Maximum Lane Rate (6.25 Gbps to 12.5 Gbps) or Low Lane Rate (3.125 Gbps to 6.25 Gbps) should be based on the Lane Line Rate that was calculated in Configuring the Board section.

    Figure 21. PLL Control

  4. Issue a Data Path Reset to the AD9680 by clicking its checkbox and clicking Apply Changes. The data path reset bit will automatically self clear.

    Figure 22. Data Path Reset

  5. If the PLL Locked indicator lights up, you can reset it by powering down the JESD link using the Link Control dropdown box, and clicking Apply Changes.

    Figure 23. PLL Lock, Link Power Down

  6. Enable the Link Control again and Apply Changes.

    Figure 24. PLL Lock, Link Enable

  7. Click Apply at AD9680 Configuration and then Proceed to Analysis. This is ACE's Analysis tool for the data from the ADC, displaying both sample plots (Waveform) and FFTs. Click on FFT and Run Once to capture once.

    Figure 25. Analysis Tool

    Figure 26. Display FFTs and Run once

    Tip: Capturing data using another program (e.g. VisualAnalog, proprietary code, etc.) while using ACE concurrently may cause errors in ACE's data capture. If this occurs, the best solution is to restart the evaluation boards and work solely via ACE, or to setup the part in ACE then capture solely in the other program.
  8. Channel A and Channel B can be selected individually to display their FFTs.

    Figure 27. Channel Selection

  9. A successful capture is shown below, with a filtered 170 MHz signal inputted at on Channel A.

    Figure 28. Example Input to Channel A

  10. To save the FFT plot, click on Export button at Analysis Results tab and save it to a location of choice.

Visual Analog & SPI Controller Configuration

Visual Analog & SPI Controller Configuration

SPI Controller Configuration

  1. Set the ADC Configuration Registers in ADCBase0 tab. Write Chip Mode Control Register address 0x200 to Full Bandwidth Mode and Chip Decimation Ratio Control Register 0x201 to Full Sample Rate.

    Figure 29. Setting Chip Mode Control and Decimation Ratio Registers

  2. For JESD204B setting, proceed to ADCBase3 tab. Check the Serial Transmit Power Down box in JESD204B Link Control Register (0x571).

    Figure 30. JESD204B Serial Transmit Power Down

  3. Set the Lane Rate setting register 0x56E to Maximum Lane Rate. The decision to use Maximum Lane Rate mode or Low Lane Rate mode should be based on the Lane Line Rate that was calculated in Configuring the Board section.

    Figure 31. Setting the JESD204B Lane Rate

  4. Set the JESD204B Quick Configuration register (0x570). For 1000MSPS operation with NO DDCs (Full Bandwidth Mode), the values for L.M.F are 4.2.1

    Figure 32. Setting the JESD204B Quick Configuration Register

  5. Proceed to ADCBase4 tab and set/read the registers 0x58B, 0x58C, 0x58D, and 0x58E to check if the desired JESD204B configurations on ADCBase3 tab are reflected.

    Figure 33. Reading the JESD204B Configuration Registers

  6. On address 0x58F (see figure 33), change the Converter Resolution to 14 for AD9680 (12 for AD9234).
  7. Back to ADCBase3 tab, uncheck the Serial Transmit Power Down box in JESD204B Link Control Register (0x571), see figure 30.
  8. After the quick configuration setting is completed, the PLL Lock Detect register 0x56F will read 0x80 to denote a lock. The SPIController interface will show a “1” to denote a lock.

    Figure 34. Reading the PLL Status Register

Obtaining an FFT on Visual Analog

  1. Click the Run button in VisualAnalog , you should see the captured data similar to the plot shown in Figure 35.

    Figure 35. AD9680-1250 FFT at 170MHz Analog Input

  2. Adjust the amplitude of the input signal so that the fundamental is at the desired level. Examine the Fund Power reading in the left panel of the VisualAnalog FFT window.
  3. To save the FFT plot do the following:
    1. Click on the Float Form button in the FFT window.

      Figure 36. Floating the FFT window

    2. Click on File right Save Form As button and save it to a location of choice.

      Figure 37. Saving the FFT

Sample Configuration 2: Two ADCs Plus Two DDCs, Decimate by 4

ACE Configuration

ACE Configuration

  1. Under Initial Configuration at board view, set the clock input to 1250 MHz. Change the Clock Divide Ratio to divide by 1. Change the Chip Operating Mode for two DDCs. The DDC settings will become available, set the Decimation Ratio select “HB1_HB2 Complex” - two half-band filters, and set the Output Select select complex. i.e. Decimate-by-4. Set the number of Lanes to 2, the number of Virtual Converters to 4, and the number of Octets per Frame to 4. Click Apply to apply the settings. Set the reference clock to 625 MHz to match these settings.

    Figure 38. DDC Chip Settings

  2. The Chip View will update to reflect the changes. Click on the NCO block to change the Numerically Controlled Oscillator's frequency to 175 MHz.

    Figure 39. NCO Frequency Setting

  3. Enable the 6dB gain for the DDC at the amplifier block drop down menu.

    Figure 40. DDC Gain

  4. Set the Mixer to Real. Click Apply Changes to apply configuration at DDC0.

    Figure 41. DDC Mixer

  5. Navigate to the second DDC (DDC1) and make the same changes.

    Figure 42. DDC Selection

  6. Set the DDC Soft Reset to DDC Held in Reset in dropdown menu to soft reset the DDC, and click Apply Changes.

    Figure 43. DDC Soft Reset

    Note: Whenever the NCO frequency is set or changed, the DDC soft reset must be issued. If the DDC soft reset is not issued, the output may potentially show amplitude variations.
  7. Change the DDC Soft Reset to Normal Operation in dropdown menu, and click Apply Changes. And then click on Proceed to Analysis.

    Figure 44. DDC Soft Reset - Normal Operation

  8. In Analysis tool, run a capture once. DDC0 can be selected from Channel A and DDC1 can be selected from Channel B (see figure 45).
  9. A successful capture is shown below, with a filtered 170 MHz signal inputted on Channel A / DDC0.

    Figure 45. Example Input to DDC0

Visual Analog & SPI Controller Configuration

Visual Analog & SPI Controller Configuration

Visual Analog & SPI Controller Configuration

  1. In the Visual Analog Software Setup, follow Steps 1-5 and after that, click the ADC Data Capture Settings, remove Ch.A and Ch.B output data, and add Ch. DDC0 and Ch. DDC1 output data.

    Figure 46. VisualAnalog ADC Data Capture Settings for DDC

  2. In the SPI Controller Software Setup, follow Steps 1-4. Set the ADC Configuration Registers in ADCBase0 tab. Write Chip Mode Control Register (0x200) to Two Digital Down Converters and Chip Decimation Ratio Control Register (0x201) to Decimate by 4.

    Figure 47. Setting Chip Mode Control and Decimation Ratio Registers

  3. For DDC Settings, proceed to ADCBase1 tab and configure DDC0 and DDC1 Control Registers with corresponding addresses of 0x310 and 0x330, respectively, to Real Mixer, Variable IF Mode, Complex (I/Q) Decimate by 4. Channel Input Selection for address 0x311 is set to Channel A for I and Q while address 0x331 is set to Channel B for I and Q.

    Figure 48. DDC Control Registers

  4. For frequency tuning word (FTW), addresses 0x314-315 are set as required by application for DDC0, and addresses 0x334-335 are set as required by application for DDC1. Figure 49 below shows the calculation for NCO Frequency Tuning Word.

    Figure 49. Frequency Tuning Word Formula

  5. After setting all DDC registers, go to Generic Write/Read in Global tab and write 0x10 to address 0x300 (DDC soft reset), and write back to 0x00 (DDC normal operation). Same process can be done by checking and unchecking the DDC Soft Reset box.

    Figure 50. DDC Synchronization Control Register

  6. For JESD204B setting, proceed to ADCBase3 tab. Check the Serial Transmit Power Down box in JESD204B Link Control Register (0x571).

    Figure 51. JESD204B Serial Transmit Power Down

  7. Set the Lane Rate setting register 0x56E to Maximum Lane Rate. The decision to use Maximum Lane Rate mode or Low Lane Rate mode should be based on the Lane Line Rate that was calculated in Configuring the Board section.

    Figure 52. Setting the JESD204B Lane Rate

  8. Set the JESD204B Quick Configuration register (0x570). For 1000 MSPS operation with 2 DDCs (Two Digital Down Converters), the values for L.M.F are 2.4.4.

    Figure 53. Setting the JESD204B Quick Configuration Register

  9. Proceed to ADCBase4 tab and set/read the registers 0x58B, 0x58C, 0x58D, and 0x58E to check if the desired JESD204B configurations on ADCBase3 tab are reflected.

    Figure 54. Reading the JESD204B Configuration Registers

  10. On address 0x58F (see figure 54), change the Converter Resolution to 14 for AD9680 (12 for AD9234).
  11. Back to ADCBase3 tab (se figure 51), uncheck the Serial Transmit Power Down box in JESD204B Link Control Register (0x571).
  12. After the quick configuration setting is completed, the PLL Lock Detect register 0x56F will read 0x80 to denote a lock. The SPIController interface will show a “1” to denote a lock.

    Figure 55. Reading the PLL Status Register

Obtaining an FFT on Visual Analog

  1. Click the Run button in VisualAnalog , you should see the captured data similar to the plot shown in Figure 56.

    Figure 56. AD9680-1000 FFT at 150.3MHz Analog Input, NCO_FTW = 155MHz

  2. Adjust the amplitude of the input signal so that the fundamental is at the desired level. (Examine the Fund Power reading in the left panel of the VisualAnalog FFT window.)

Validating Deterministic Latency Using Subclass 1 Operation

The following .zip files contain the files needed for users to validate subclass 1 operation and observe the latency differences between subclass 0 and subclass 1 operation. The “Validating Subclass 1 Operation of the AD9680” document will guide the user through the necessary steps to perform this validation. SPI Controller scripts for several full bandwidth modes are included for convenience.

Troubleshooting Tips

Evaluation board is not functioning properly

  • It is possible that a board component has been rendered inoperable by ESD, accidental shorting while probing, etc. Try checking the supply domain voltages of the board while it is powered. They should be as follows:
  • Domain Test Point Approx. Voltage
    AVDD_1 TP406 1.25 V
    AVDD_1 TP106 1.25 V
    AVDD_2 TP404 2.50 V
    AVDD_1P8 TP401 1.80 V
    DVDD TP407 1.25 V
    DRVDD TP410 1.25 V
  • If a short is detected between any of the supply domains and ground, or an open is detected across fuse chip F400 or F401, a component may have been damaged.

Evaluation board is not communicating with the ADS7-V2 / No SPI communication

  • Make sure that the FPGA on the ADS7-V2 has been programmed - a lit LED DS15 (FPGA_DONE) on the top of the ADS7-V2 and a powered fan are good indicators of the FPGA being programmed.
  • Check the common mode voltage on the JESD204B traces. On the evaluation board, the common mode voltage should be roughly two-thirds of DRVDD_1. On the ADS7-V2, the common mode voltage should be around 1.2 volts.
  • To test SPI operation, attempt to both read and write to register 0x00A (Scratch Pad) using ACE's Register Debugger (Tools → Register Debugger). This register is an open register available for testing memory reads and writes. If the register reads back the same value written to it, SPI is operational.
  • All registers reading back as either all ones or all zeros (i.e., 0xFF or 0x00) may indicate no SPI communication.
  • Register 0x000 (SPI Configuration A) reading back 0x81 in ACE may indicate no SPI communication as a result of the FPGA on the ADS7-V2 not being programmed.

ACE software fails to capture date

  • Ensure that the board is functioning properly and that SPI communication is successful - see previous troubleshooting tips.
  • Check the Clock Status register 0x011C to see if the input sample clock is being detected. 0x01 indicates detection, 0x00 indicates no clock detected. Check the signal generator input on connector J801. Try checking the common mode voltage on the clock pins, which should be roughly two-thirds of AVDD_1. Try placing a differential oscilloscope probe on the clock pins to see if the clock signal is reaching the chip.
  • Check the PLL Locked indicator (see figure 23) or register 0x056F (PLL Status). If the light in the plugin chip view is green or if the register reads back 0x80, the PLL is locked. If it is not locked:
    • Check the clock being input to connector J801 (in this guide, 1.25 GHz or 1 GHz depending on the evaluation board).
    • Check the JESD204B settings under the Initial Configuration. Reference the AD9680 / AD9690 / AD9234 datasheet for supported lane options.
    • Check the Reference Clock and make sure it matches your JESD settings.
    • Make sure P100 (Power Down / Standby Jumper) is not jumped.

VisualAnalog displays a blank FFT when the RUN button is clicked

  • Ensure that the clock to the ADC is supplied. Using SPIController ADCBase0 tab the status of the clock can be read out. See figure 57.

    Figure 57. Clock Detection Status Register

  • Ensure that the ADC's PLL is locked by checking the status of the PLL lock detect register 0x56F. This can be done using SPIController (see figure 34 or 55).

VisualAnalog indicates that the “FIFO capture timed out” or “FIFO not ready for read back”

  • Make sure all power and USB connections are secure.
  • Make sure that the Reference Clock is ON and set to the appropriate frequency.

FFT plot appears abnormal

  • If you see a normal noise floor when you disconnect the signal generator from the analog input, be sure you are not overdriving the ADC. Reduce input level if necessary.
  • In ACE Analysis tab under CAPTURE → General → Encoding (see figure 26), check that the encoding is set to correct number format (two's compliment by default).
    • Issue a Data Path Reset through ACE Chip View (see figure 22).
  • In VisualAnalog, Click on the Settings button in the Input Formatter block. Check that Number Format is set to the correct encoding (twos compliment by default). Repeat for the other channel.
    • Issue a Data Path Soft Reset through SPIController Global tab (see Figure 23).

The FFT plot appears normal, but performance is poor.

  • Make sure you are using the appropriate band-pass filter on the analog input.
  • Make sure the signal generators for the clock and the analog input are clean (low phase noise).
  • If you are using non-coherent sampling, change the analog input frequency slightly, or use coherent frequencies.
  • Make sure the SPIController config file matches the product being evaluated when using the VisualAnalog.

The FFT window remains blank after the Run button is clicked

  • Make sure the evaluation board is securely connected to the ADS7-V2.
  • Make sure the FPGA has been programmed by verifying that the Config DONE LED is illuminated on the ADS7-V2. If this LED is not illuminated restart the ACE software to reload the FPGA program, or reprogram the FPGA through VisualAnalog if not using the ACE software. If the LED still does not illuminate disconnect the USB and power cord for 15 seconds. Connect again and repeat the ADS7-V2 setup process.
    • Make sure the correct FPGA bin file was used to program the FPGA in VisualAnalog.
  • Be sure that the correct sample rate is programmed.
    • In ACE, check the Board view tab and Chip view tab if the Sampling Frequency is properly set (see figures 8 & 9)
    • In VisualAnalog, click on the Settings button in the ADC Data Capture block. Verify that the Clock Frequency is properly set (see figure 14).
  • Ensure that the Reference Clock is ON and set to the appropriate frequency.
  • Restart ACE software or VisualAnalog/SPIController.
resources/eval/ad9680-1000ebz.txt · Last modified: 23 Oct 2023 08:25 by Janadrian Alipio

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